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Method for verifying IP core, device and system

A technology to be verified and verified results, which is applied in the field of verifying IP cores, can solve the problems of low efficiency in the IP core verification process, and achieve the effect of avoiding long development time, avoiding poor flexibility, and improving verification efficiency

Active Publication Date: 2021-07-27
BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY +5
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main purpose of the present invention is to provide a method, device and system for verifying IP cores, aiming to solve the problem of low efficiency in the verification process of IP cores in the prior art

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  • Method for verifying IP core, device and system
  • Method for verifying IP core, device and system
  • Method for verifying IP core, device and system

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Embodiment Construction

[0065] The specific implementation manners of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation manners described here are only used to illustrate and explain the embodiments of the present invention, and are not intended to limit the embodiments of the present invention.

[0066]It should be noted that if there are directional indications (such as up, down, left, right, front, back...) in the implementation of the present application, the directional indications are only used to explain the position in a certain posture (as shown in the attached figure). If the specific posture changes, the directional indication will also change accordingly.

[0067] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second" and so on are only for descriptive purposes...

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Abstract

The invention discloses a method for verifying an IP core, a device and a system thereof. The method comprises the following steps: generating test data through a control board card; sending the test data to a verification board card, so that the verification board card performs read-write access operation on the target memory based on an IP core in the verification board card and the test data; obtaining first data read by the verification board card from the target memory; and obtaining a verification result according to the test data and the first data. The test data is generated in the control board card, and the verification board card is controlled according to the program in the control board card to realize read-write verification of the IP core, so that the defects of long development time and poor flexibility caused by the fact that hardware verification personnel need to write a hardware verification language in traditional IP core verification are avoided, and the verification efficiency of the IP core is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a method, device and system for verifying IP cores. Background technique [0002] Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, DDR SDRAM) is a new type of memory chip developed on the basis of SDRAM chip, which is called DDR for short. The biggest feature of DDR is that it has a double data transmission rate, that is, data transmission can be performed on both the rising and falling edges of the clock. DDR has experienced several generations of development, from the initial DDR1 to DDR2, DDR3, the transmission rate and storage capacity have been continuously improved. [0003] The IP core is usually used to control the DDR memory for read and write operations. At present, the verification of the IP core is generally realized through simulation and testing with a verification system. The specific process refers to the simulation ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F11/263
CPCG06F11/2236G06F11/2273G06F11/263
Inventor 周芝梅陈禾谢宜壮王晓勇田安琪马良冯晨万勇熊奎
Owner BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY