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Memory controller and data processing method

A memory controller and memory technology, applied in the field of data processing, can solve the problems of reducing the access speed of flash memory, reducing the access speed of memory, occupying memory space, etc.

Active Publication Date: 2021-08-06
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, since the parity information must be stored in the flash memory, the actual memory space available for storing valid data in the flash memory will be reduced due to the application of the protection mechanism
In addition, the calculation, storage, and reading operations of the same bit information will waste the computing resources of the flash memory controller, further reducing the access speed of the flash memory
[0005] In order to solve the above-mentioned problems, a novel data processing method is needed, which can effectively protect the data stored in the memory device, and at the same time avoid the above-mentioned problems of occupying memory space and reducing memory access speed, etc.

Method used

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Embodiment Construction

[0035] figure 1 is a block diagram showing a system according to an embodiment of the present invention. The system may be a data storage system, a computer system or an electronic product system. The system 100 may include a host device 110 and a storage device 120 . The storage device 120 may include a memory controller 121 and one or more memory devices. According to an embodiment of the present invention, the storage device 120 may be a solid state drive (SSD) installed in or connected to the electronic product. The memory controller 121 may be coupled to the one or more memory devices, wherein the memory device may be a dynamic random access memory (Dynamic Random Access Memory, DRAM for short) 122 and a flash memory (Flash memory) shown in the figure. 123, and the flash memory 123 may include a plurality of flash memory modules. The memory controller 121 can access the DRAM 122 and the flash memory 123 through corresponding interfaces. The memory controller 121 also...

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Abstract

The invention discloses a memory controller and a data processing method. The memory controller comprises a memory interface and a processor. The processor is coupled to the memory interface and used for controlling access operation of a memory device through the memory interface. The processor maintains a predetermined table according to a write operation of a first memory block of the memory device, and performs data protection in response to the write operation. When the data protection is executed, the processor judges whether the storage space of the first memory block is damaged or not. When it is determined that the storage space of the first memory block is damaged, the processor traces one or more data sources corresponding to the data written into the first memory block according to a predetermined table to obtain address information of one or more source memory blocks, and performs a data repair operation according to the address information of the one or more source memory blocks.

Description

technical field [0001] The invention relates to a data processing method, in particular to a data processing method capable of effectively protecting data stored in a memory device. Background technique [0002] Due to process factors in flash memory devices, a certain percentage of memory cells will be physically damaged before their guaranteed lifespan, making the memory cells unusable. If the storage unit has been written with valid data when the damage occurs, it will further cause loss of valid data. [0003] In order to protect the flash memory from loss of valid data due to the damage of the storage unit, the protection mechanism adopted by the fault-tolerant disk array (Redundant Array of Independent Disks, abbreviated as RAID) is used in the existing technology to protect the data of the flash memory. Protect. In the protection mechanism adopted by RAID, parity information is calculated according to the data written into the flash memory, and the parity informatio...

Claims

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Application Information

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IPC IPC(8): G06F3/06G06F11/14G06F12/02G06F12/0802
CPCG06F3/0622G06F3/0619G06F3/064G06F3/0658G06F3/0647G06F3/0656G06F3/0679G06F12/0246G06F12/0802G06F11/1435
Inventor 许维仁陈致谚陈彦仲潘俊忠
Owner REALTEK SEMICON CORP
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