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DFT test device, DFT test system and DFT test method

A test device and clock gating technology, applied in electronic circuit testing, integrated circuit testing, etc., can solve the problems of loss of test coverage and reduced test efficiency, etc.

Active Publication Date: 2021-08-10
成都爱旗科技有限公司
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Problems solved by technology

[0005] The object of the present invention is to provide a kind of DFT test device, test system and test method, be used for chip test, when adopting to increase the number of test vectors, when solving the problem of loss test coverage, can cause the technical problem that test efficiency reduces

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  • DFT test device, DFT test system and DFT test method
  • DFT test device, DFT test system and DFT test method

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[0048] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their sequence is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the number and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0049] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "ex...

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Abstract

The invention discloses a DFT test device, a test system and a DFT test method, relates to the technical field of chip testing, and aims to solve the technical problem that the testing efficiency is reduced when the problem of testing coverage rate loss is solved by increasing the number of testing vectors. The DFT test device comprises a control unit and a clock gating unit. The input end of the control unit is electrically connected with a scanning enable signal end, the output end of the control unit is electrically connected with the test enable end of a clock gating unit, and the enable end of the clock gating unit is electrically connected with a function logic signal end. In the shifting stage, a first signal is provided for the control unit, and the control unit outputs a first control signal to control the clock gating unit to be opened. In the capturing stage, a second signal is provided for the control unit, and a second control signal and a functional logic signal output by the control unit control the clock gating unit to be opened or closed. The test system comprises the DFT test device provided by the technical scheme. The DFT test device provided by the invention is used for chip testing.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a DFT testing device, a testing system and a DFT testing method. Background technique [0002] With the rapid development of integrated circuits, the integration of chips is getting higher and higher, resulting in more and more complex logic scales and working modes. Design for test based on chip level (Design for test, abbreviated as DFT) is becoming more and more important. . [0003] In the existing DFT test solution, the industry's handling of the test enable terminal (TestEnable, abbreviated as TE) of clock gating (Clock Gating) is relatively simple, and the test coverage will be lost, and there is a risk of missed testing. [0004] At present, the problem of loss of test coverage is solved by increasing the number of test vectors. However, increasing the number of test vectors will lead to a decrease in test efficiency. Contents of the invention [0005] The objec...

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/287
Inventor 李仲勋
Owner 成都爱旗科技有限公司
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