Voltage margin enhanced capacitive coupling storage and calculation integrated unit, sub-array and device
A capacitive coupling and voltage margin technology, which is applied in the field of sub-arrays and devices, and the voltage margin enhanced capacitive coupling storage and computing integrated unit can solve the problems of high power consumption, long charging and discharging time, and large computing power consumption. , to achieve the effect of reducing power consumption
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Embodiment 1
[0047] Such as figure 1 As shown, the present invention discloses a voltage margin-enhanced capacitive coupling storage and calculation integrated unit, the unit includes: a 6T-SRAM storage unit and a computing unit; the computing unit is connected to the 6T-SRAM storage unit; the The word line end of the 6T-SRAM memory cell is connected to the word line, the bit line end of the 6T-SRAM memory cell is connected to the bit line, and the reverse bit line end of the 6T-SRAM memory cell is connected to the reverse bit line; The input line end of the calculation unit is connected to the input line, the column selection line end of the calculation unit is connected to the column selection line; the read bit line end of the calculation unit is connected to the read bit line; the input line is used to transmit input data ; The 6T-SRAM storage unit is used to read, write and store the weight value; the calculation unit is used to multiply the input data and the weight value.
[0048] ...
Embodiment 2
[0065] Such as Figure 6 As shown, the present invention discloses a voltage margin-enhanced capacitively coupled storage and calculation integrated sub-array, the sub-array includes: K units described in Embodiment 1; K is a positive integer greater than or equal to 2; The word line, bit line, reverse bit line, input line and column selection line are connected, the read bit line is connected to the source of the transistor T12 in the first calculation unit, and the drain of the transistor T12 in the kth calculation unit is connected to the first transistor T12 in the calculation unit. There are k+1 source connections of the transistor T12 in the calculation unit, wherein k is a positive integer greater than or equal to 1 and less than K. In this embodiment, K is 4.
[0066] The principle of pressure equalization: such as Figure 7 As shown, after the input data is multiplied by the weight value, the calculation results are expressed as the voltages at both ends of the coup...
Embodiment 3
[0068] Such as Figure 8 As shown, the present invention also discloses a voltage margin enhanced capacitive coupling storage and calculation integrated device, which includes: a first input module, a second input module, a third input module and a computing unit array; the first input The module is a word line decoding and driving module ①; the second input module is a column decoding, bit line driving and pre-storage module ②; the third input module is an input decoding and driving module ④; the computing unit array The sub-array ③ described in Embodiment 2 comprising M×N arrays, wherein, M is a positive integer greater than 1, and N is a positive integer greater than 1.
[0069] The M word line ends of the first input module are respectively connected to M word lines; the N column selection line ends of the second input module are respectively connected to N column selection lines, and the bits of the second input module The line end is connected to the bit line, and the r...
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