An ultra-low power fast transient response low dropout linear regulator circuit

Abstract

The invention discloses an ultra-low power consumption fast transient response low dropout linear voltage regulator circuit, comprising a first self-bias circuit, an error amplifier, a second self-bias circuit, a buffer, an N-type power tube, a first A compensation network, a second compensation network and a self-bias transistor, the tail current terminal of the error amplifier is connected to the first self-bias circuit, the control terminal of the first self-bias circuit is connected to the output terminal of the error amplifier, so The buffer is connected to the second bias circuit, the control terminal of the second self-bias circuit is connected to the output terminal of the error amplifier, the source of the N-type power tube is connected to the drain of the self-bias transistor, so The first compensation network is respectively connected with the error amplifier and the N-type power tube, and the second compensation network is connected with the error amplifier. The invention improves its transient response capability by widening the loop bandwidth of the low-dropout linear regulator and increasing the slew rate of the grid of the power tube. The present invention can be widely used in the technical field of integrated circuits.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an ultra-low power consumption fast transient response low dropout linear voltage regulator circuit. Background technique [0002] Low drop-out voltage regulator (LDO) has the advantages of small ripple, simple structure, small area and low cost. The power supply voltage is widely used in portable small smart products. In portable electronic products, the battery is the only energy source. Therefore, in order to reduce the energy consumption and prolong the working time of the battery, low power consumption has become its main research direction. The traditional LDO regulator consists of an error amplifier, PMOS power transistor and resistor feedback network. In order to obtain a larger loop gain, the output impedance of the error amplifier is often relatively large; due to the need to increase the size of the power tube to increase the load capacity of the LDO chip...

AI Technical Summary

Problems solved by technology

In order to obtain a larger loop gain, the output impedance of the error amplifier is often relatively large; since it is necessary to increase the size of the power transistor to increase the load capacity of the LDO chip, the parasitic capacitance of the gate of the power transistor will also increase accordingly. Therefore, the pole formed by the gate capacitance of the power tube and the high output impedance of the error amplifier will be relatively low. At this time, the output pole formed by the output impedance of the output terminal and the off-chip capacitance will also be relatively low. After the compensation is stable, the two lower poles will be Severely weaken the loop bandwidth of the LDO, which is not conducive to the load transient response of the LDO

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