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Verification method, device, device and readable storage medium of algorithm module in chip

A technology of algorithm module and verification method, which is applied in the directions of calculation, instrumentation, error detection/correction, etc., can solve the problems of inability to quickly and effectively locate the error position and inconvenient use, so as to ensure timing consistency, reduce workload, and improve verification efficiency effect

Active Publication Date: 2022-07-29
SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Calling the C interface function needs to be called at a specific moment, and it needs to be called multiple times, which is inconvenient to use. When the chip algorithm module fails to pass the verification, it is impossible to quickly and effectively locate the error position

Method used

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  • Verification method, device, device and readable storage medium of algorithm module in chip
  • Verification method, device, device and readable storage medium of algorithm module in chip
  • Verification method, device, device and readable storage medium of algorithm module in chip

Examples

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Embodiment 1

[0073] see figure 1 , figure 1 It is an implementation flow chart of a verification method for an algorithm module in a chip in an embodiment of the present invention, and the method may include the following steps:

[0074] S101: Parse the received algorithm module verification request to obtain a target algorithm module to be verified.

[0075] When the algorithm module in the chip needs to be verified, an algorithm module verification request is sent to the pre-built chip algorithm module verification platform. The algorithm module verification request can include the target algorithm module to be verified, the chip information to which the target algorithm module belongs, etc. The chip algorithm module verification platform receives the algorithm module verification request, parses the received algorithm module verification request, and obtains the target algorithm module to be verified.

[0076] S102: Retrieve the target SystemC reference model corresponding to the pre-...

Embodiment 2

[0089] see figure 2 , figure 2 It is another implementation flow chart of the verification method of the algorithm module in the chip in the embodiment of the present invention, and the method may include the following steps:

[0090] S201: Parse the received algorithm module verification request to obtain a target algorithm module to be verified.

[0091] S202: Retrieve the target SystemC reference model corresponding to the pre-built target algorithm module.

[0092] see image 3 It is a structural block diagram of a SystemC reference model corresponding to a compression algorithm module in an embodiment of the present invention. When the target algorithm module is a compression algorithm module, the compression algorithm module looks for repeated parts in the input original text and replaces these repeated parts with a specific code, thereby replacing a longer text with a shorter code. , so as to compress the input. The SystemC reference model mainly includes hash ca...

Embodiment 3

[0169] Corresponding to the above method embodiments, the present invention also provides a verification device for an algorithm module in a chip. The verification device for an algorithm module in a chip described below and the verification device method for an algorithm module in a chip described above can refer to each other correspondingly. .

[0170] see Image 6 , Image 6 It is a structural block diagram of an apparatus for verifying an algorithm module in a chip in an embodiment of the present invention, and the apparatus may include:

[0171] The request parsing unit 61 is used for parsing the received algorithm module verification request to obtain the target algorithm module to be verified;

[0172] The model retrieval unit 62 is used to retrieve the target SystemC reference model corresponding to the pre-built target algorithm module;

[0173] The use case input unit 63 is used to obtain each test case corresponding to the target algorithm module through a prese...

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Abstract

The invention discloses a verification method for an algorithm module in a chip, which comprises the following steps: parsing a verification request of an algorithm module to obtain a target algorithm module to be verified; retrieving a target SystemC reference model corresponding to the target algorithm module; obtaining through a preset input agent Each test case corresponding to the target algorithm module, and input each test case to the target SystemC reference model and the target algorithm module according to the preset time sequence; use the output agent to obtain the output of each level of the target SystemC reference model and the target algorithm module respectively; The outputs of all levels are compared correspondingly, and the verification results of the target algorithm module are obtained. The invention ensures the time sequence consistency of the target SystemC reference model and the target algorithm module, greatly reduces the workload and improves the verification efficiency. The invention also discloses a device, equipment and storage medium, which have corresponding technical effects.

Description

technical field [0001] The present invention relates to the technical field of computer applications, and in particular, to a verification method, apparatus, device and computer-readable storage medium of an algorithm module in a chip. Background technique [0002] With the continuous development of the System on Chip (SOC) technology, the complexity of the design continues to increase, which greatly increases the complexity of the SOC verification, and the verification accounts for a large proportion of the entire SOC development process time. In particular, the SOC of the algorithm class contains complex algorithms, which makes the design verification of the chip quite complicated. [0003] The verification of the algorithm module in the chip requires a corresponding algorithm reference model. The traditional reference model is generally implemented in C language or C++ language. Advanced programming languages ​​such as C and C++ have high abstraction capabilities, but bec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36
CPCG06F11/3688G06F11/3692G06F11/3676G06F11/3684
Inventor 李靖蕙邵海波祁鹏展
Owner SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD