Calibration controller for DDR3 storage protocol

Abstract

The invention discloses a DDR3 storage protocol-oriented calibration controller, abandons a traditional clock control circuit and adopts a negative feedback structure to reduce the influence of the process, temperature and noise on a clock. The controller comprises a digital delay phase-locked loop, a mirror image multi-phase delay chain, a multi-phase selector and a high-precision phase interpolator, so accurate control, relatively low phase error and relatively short locking time on a clock are realized. According to the calibration controller for the DDR3 storage protocol, accurate delay of 128-level TAP of a DDR3 clock can be achieved under the condition that the highest frequency is 800 MHz, the highest delay accuracy can reach 9.77ps, the central position of a sampling clock delay data effective window is guaranteed, and sampling stability and reliability of the DDR3 high-frequency clock are improved.

Description

technical field [0001] The invention relates to a calibration controller oriented to a DDR3 storage protocol, in particular to a clock control circuit optimized for DDR3 application requirements through a programmable logic device, belonging to the field of integrated circuits. Background technique [0002] DDR3 SDRAM adopts a more advanced production process on the basis of DDR2 SDRAM, its working voltage is reduced from 1.8V to 1.5V, and using a more advanced process, its memory data transfer rate has been greatly improved, up to 1600MHz, which can meet the Demand for high-performance servers while enabling fast, stable and reliable system operation [0003] In DDR3 SDRAM, the data is doubled, and the data sampling clock can reach up to 800MHz, that is, both the rising and falling edges of the data clock are sampled at the same time. Therefore, how to quickly and accurately locate the sampling clock in the DDR3 SDRAM controller is very important. Whether the accurate samp...

AI Technical Summary

Problems solved by technology

[0004] The technical problem solved by the present invention is: for the internal clock of the DDR3 memory and the external clock have a deviation, a clock calibration technology for the DDR3 storage protocol is provided, which overcomes the shortcomings of the existing technology and solves the problems in the DDR3 memory caused by temperature and voltage fluctuations. The problem of external clock asynchronization improves the performance of the delay line, solves the problem of precise delay of DDR3 clock 128-level TAP, solves the problem of poor sampling accuracy of DDR3 calibration controller, and solves the problem of poor anti-interference ability and locking of DDR3 calibration controller long time problem

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