Device and method for parallelizing and simulating in-memory computation based on frequency division multiplexing

Abstract

The invention discloses a device for parallelizing and simulating in-memory computation based on frequency division multiplexing. The device comprises an input circuit, a memory array and an output circuit; the input of the memory array is connected with the output of the input circuit, and the output of the memory array is connected with the input of the output circuit; the input circuit modulates k data in each row of m * k input signal data into one path of frequency division multiplexing signal by adopting k different frequency sources and outputs the frequency division multiplexing signal; the memory array comprises m * n memory elements, weights are stored to form an m * n matrix, and m * 1 input frequency division multiplexing signals are processed in parallel in the memory array; the output circuit demodulates and separates each path of frequency division multiplexing signal output by the memory array into k data. The invention further discloses a method for parallelizing analog in-memory computation based on frequency division multiplexing. Parallel in-memory calculation is achieved in the same memory array, multiplication of matrixes in a calculation period is achieved, and the hardware utilization efficiency, the system energy efficiency ratio and the calculation density are improved.

Description

technical field [0001] The invention relates to a device and method for in-memory computing, in particular to a device and method for simulating in-memory computing based on frequency division multiplexing parallelization. Background technique [0002] When the von Neumann architecture faces high-performance computing tasks such as artificial intelligence algorithms, its storage-computing separation architecture causes a lot of energy waste and reduced computing efficiency. The memory array can be used to perform in-memory calculations. The difference from the previous Von Neumann computing architecture is that it uses analog signals to complete the calculation process in the memory array. This new type of computing architecture has great advantages in terms of power consumption and speed, and is a new type of computing architecture focused on research and development in the post-von Neumann era. According to the existing data, the above-mentioned existing in-memory computi...

AI Technical Summary

Problems solved by technology

Solve the problem that the existing parallelization scheme requires multiple sets of the same memory array; solve the excessive chip area and high system power consumption caused by the existing parallelization scheme, and the duplication of the hardware process of the existing parallelization scheme on the yield and uniformity Questions with high requirements such as parameters

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