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Network layer communication method between a central processing unit (CPU) and field programmable gate array (FPGA)

A communication method and network layer technology, applied in the direction of electrical components, transmission systems, etc., can solve problems such as the end of transmission that cannot be solved

Active Publication Date: 2021-09-14
SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, some FPGAs and CPUs on the market based on the SDIO / eMMC protocol can only be used as the host due to limitations, and the end of the communication can only be judged by the CPU. When the FPGA needs to transmit data to the CPU, it cannot be solved according to the standard SDIO / eMMC protocol command. How does the CPU judge the end of the FPGA transmission

Method used

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  • Network layer communication method between a central processing unit (CPU) and field programmable gate array (FPGA)
  • Network layer communication method between a central processing unit (CPU) and field programmable gate array (FPGA)
  • Network layer communication method between a central processing unit (CPU) and field programmable gate array (FPGA)

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Embodiment 1

[0057] A kind of network layer communication method between CPU and FPGA of the present invention, see figure 1 As shown, it is applied to the communication between CPU and FPGA. In the present invention, CPU acts as a host, and FPGA acts as a device for data communication. Either the host CPU or the device FPGA can initiate communication for data transmission.

[0058] Such as figure 1 As shown, the communication interface between the host CPU and the device FPGA is defined as follows:

[0059] 1) IO1: used for the device FPGA to wake up the host CPU line;

[0060] 2) IO2: used for the host CPU to wake up the device FPGA line;

[0061] 3) CMD: command control line, the host CPU sends commands to the device FPGA through this line;

[0062] 4) D0~D7: data lines, used to transmit data;

[0063] 5) CLK: Clock signal line, used to send the clock signal from the host CPU to the device FPGA.

[0064] Such as figure 2 As shown, the interactive data defining the host CPU and t...

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Abstract

The invention discloses a network layer communication method between a central processing unit (CPU) and a field programmable gate array (FPGA), which comprises the following steps that: a host CPU or an equipment FPGA transmits data to a communication opposite side according to an SDIO / eMMC protocol, and performs single-frame and multi-frame transmission according to the transmitted data volume; and a data frame in the data transmission process comprises protocol control information and data, the protocol control information comprises frame types, and the frame types are used for distinguishing different frames in a single frame and multiple frames. On the basis of the SDIO / eMMC protocol, a layer of data frame format is packaged again, so that reliable transmission of big data is realized.

Description

technical field [0001] The invention belongs to the technical field of network layer communication, relates to the network layer communication between FPGA and CPU based on SDIO / eMMC protocol, and specifically relates to a network layer communication method between CPU and FPGA. Background technique [0002] FPGA (Field Programmable Gate Array) is a product of further development on the basis of programmable devices such as PAL and GAL. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. [0003] The central processing unit (CPU for short) is the computing and control core of the computer system and the final execution unit for information processing and program operation. Since the CPU was produced, it has made great progress in logic structure, operating efficiency and f...

Claims

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Application Information

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IPC IPC(8): H04L29/06H04L29/08
CPCH04L69/03H04L69/325Y02D10/00
Inventor 吴凡张磊汪健赵忠惠张瑾余向阳徐叔喜刘源王佚楠曾鑫
Owner SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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