A synchronization method and system based on ATE chip testing
A chip testing and synchronizing system technology, applied in fault hardware testing methods, detecting faulty computer hardware, error detection/correction, etc. Time-saving, fast-synchronized effects
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Embodiment 1
[0034] A synchronization system based on ATE chip testing, including a main control board, N service boards and a backplane, where N is a positive integer; the service board communicates with the main control board through the backplane; the main control board includes a main control CPU and a main control board FPGA, the business board includes the business board FPGA, and the business board FPGA includes the FPGA chip test execution module; the main control CPU main program sends the chip test program to the main control FPGA, the main control FPGA sends the test program to the FPGA chip test execution module, and the main control FPGA sends the test program to the FPGA chip test execution module. Send the test program to the FPGA chip test execution module.
[0035] By setting the FPGA chip test execution module on the service board FPGA, the test result judgment action is realized synchronously in the service board, thereby improving the chip test efficiency and reducing th...
Embodiment 2
[0043] A synchronization method based on ATE chip testing, including a synchronization system for ATE chip testing, according to appendix Figure 4 It can be seen that the synchronization method is,
[0044] When the test is started, the main control CPU sends the chip test program to the main control FPGA, the main control FPGA sends the chip test program to the business board, and the FPGA chip test execution module on the business board starts the chip test synchronously;
[0045] Test operation, the FPGA chip test execution module of the business board FPGA runs the chip test program;
[0046]The chip test result is determined, and the FPGA chip test execution module of the business board FPGA judges the chip test result. If the chip test result is successful, the chip test result signal is set high, otherwise the chip test result signal is set low;
[0047] The test results are synchronized, and the FPGA chip test execution module synchronizes the chip test results to th...
Embodiment 3
[0049] On the basis of the above embodiment, this embodiment further includes analysis of test results, the main control board FPGA synchronizes the chip test results of the service boards, and determines the chip test results of multiple service boards.
[0050] Analysis of the test result, the test result signal received by the main control board FPGA and the preset synchronization register are bit-wise ORed to obtain the result signal, whether the result signal is all high level, if all high level, the service board chip test is successful; otherwise The service board chip test fails, and the test results are fed back to the corresponding service board FPGA.
[0051] The test program is a test program with FPGA chip test instructions; if the chip test result is successful, the business board FPGA continues to execute the subsequent test program; if the chip test result fails, the business board FPGA feeds back the test result to the main program of the main control CPU.
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