Chip performance test system and test method
A chip performance and test system technology, applied in the field of optical communication, can solve the problems of low test efficiency and poor accuracy, and achieve the effect of solving low test efficiency
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0055] In order to solve the technical problems of low test efficiency and poor accuracy in traditional test schemes, an embodiment of the present invention provides a chip performance test system, such as Figure 1-Figure 5 As shown, it mainly includes a chip holder 101 , a test bench 201 , a controller, an imaging system connected to the controller, a DC probe 301 , a high frequency probe 401 and an optical fiber 501 . in:
[0056] The chip holder 101 is used to clamp the chip 100 to be tested, and the chip holder 101 is placed on the test bench 201 to perform the performance test of the chip to be tested 100; the imaging system is located above the test bench 201 , for collecting the image of the chip under test 100; when performing a performance test, the DC probe 301, the high frequency probe 401 and the optical fiber 501 are in contact with the chip under test 100 respectively, for The chip 100 to be tested provides a DC signal, a high frequency signal and an optical si...
Embodiment 2
[0072] On the basis of the above-mentioned embodiment 1, the embodiment of the present invention further provides a chip performance testing method, which can be completed by using the testing system in the embodiment 1. Such as Figure 10 As shown, the test method mainly includes the following steps:
[0073] Step 1: After the chip to be tested 100 is clamped by the chip holder 101, the chip holder 101 is placed within the collection range of the imaging system, and the image of the chip to be tested 100 is collected by the imaging system and fed back to the controller .
[0074] combine Figure 4 with Figure 5 , first move the first moving baffle 1011 and the second moving baffle 1012 outwards, and push the elastic piece 1013 outward; then place the chip 100 to be tested on the first Moving baffle 1011, the second moving baffle 1012, the elastic piece 1013 and the storage space formed by the fixed baffle 1014; The second moving baffles 1012 all move inward, and limit t...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 



