Jitter tolerance adjustable non-reference clock frequency detection circuit

Abstract

The invention discloses a jitter tolerance adjustable non-reference clock frequency detection circuit, which is characterized in that a data signal port of a D trigger receives differential clock signals CK and CKB, and a clock input port of the D trigger receives differential input signals DATA and DATAB; the output end of the D trigger generates output signals Q and QB and is connected to the input end of the low-pass filter, and the low-pass filter generates output signals Q'and QB' subjected to low-pass filtering; the first input end of the signal peak detection circuit is connected with the output end of the low-pass filter, the second input end of the signal peak detection circuit is connected with the output end of the reference voltage generator, and reference voltage Vref is received; and the signal peak value detection circuit outputs a digital signal according to the signal peak values of the Q' and the QB' and the reference voltage Vref.

Description

technical field [0001] The invention relates to the field of communication systems, in particular to a reference clock frequency detection circuit with adjustable jitter tolerance. Background technique [0002] In high-speed wired communication systems, in order to reduce costs, the data transmitted between the transmitter and receiver is usually sent and received without a clock signal. For example, in optical communication, high-speed data transmission and reception is not accompanied by a clock signal. In this case, the receiver is required to have a clock and data recovery circuit (Reference-less CDR) without a reference clock. [0003] The clock and data recovery circuit has the following functions: recover the clock synchronized with the frequency and phase of the received signal from the data without the accompanying clock; recover the data from the data without the accompanying clock, reduce the signal jitter, and improve the signal quality. Phase-locked loop (PLL)...

AI Technical Summary

Problems solved by technology

Phase-locked loop (PLL) is widely used in CDR circuit design, but its own narrow frequency capture range cannot meet the requirements of communication systems

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