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Chip testing method, testing machine and storage medium
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A technology of chip testing and testing machine, which is applied in the direction of electronic circuit testing, measuring electronics, and measuring devices. Current, the effect of improving accuracy
Active Publication Date: 2021-10-19
绅克半导体科技(苏州)有限公司
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Then when each chip is tested, the combination of the voltage difference between each pin and the test channel of the tester will also be diverse, which will cause random deviations in the low power consumption current when different chips are tested, thus affecting mass production yield and Consistency Analysis of Data Distribution
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Embodiment 1
[0045] This embodiment discloses a chip testing method, which is used to measure the static operating current of the chip under test in low power consumption mode through a test machine, and the test machine includes a programmable power supply (DPS) for supplying power to the chip under test , and a plurality of test channels 10 connected to each tested pin of the chip under test (DUT), refer to image 3 .
[0046] The chip testing method comprises the following steps:
[0047] S1. Configure the chip under test in a low power consumption mode; optionally, configure the chip under test in a low power consumption mode through a test vector.
[0048] S2. Configuring each measured channel corresponding to each measured pin to be in a high-impedance mode.
[0049] S3. Obtain the first measured voltage of each measured pin in the high-impedance mode at this time; refer to image 3 , wherein the first measured voltage of the tested pin Pin#1 is V1, the first measured voltage of t...
Embodiment 2
[0061] This embodiment discloses a testing machine, which is used to execute the chip testing method described in Embodiment 1. The testing machine includes:
[0062] Programmable power supply for powering the chip under test;
[0063] A plurality of test channels are connected to each tested pin of the tested chip;
[0064] a test unit, configured to obtain the first measured voltage measured on the test channel;
[0065] The configuration unit is configured to generate a background driving voltage according to the measurement signal obtained by the testing unit, and configure the corresponding test channel with the background driving voltage, and the background driving voltage is used to offset the corresponding first measured voltage .
[0066] Wherein, the configuration unit is further configured to configure the multiple test channels into a high-impedance mode before measuring the first measured voltage.
[0067] The test unit is also used to measure the chip under te...
Embodiment 3
[0069] This embodiment discloses a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the chip testing method described in the first embodiment are implemented.
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Abstract
The invention relates to the technical field of chip testing, and discloses a chip testing method, the chip testing method is used for measuring the static working current of a tested chip in a low power consumption mode, a testing machine comprises a programmable power supply used for supplying power to the tested chip and a plurality of testing channels connected to tested pins of the tested chip, the method comprises the following steps of: configuring the tested chip into a low-power-consumption mode; configuring each testing channel corresponding to each tested pin to be in a high-resistance mode; acquiring a first tested voltage of each tested pin in a high-resistance mode at the moment; generating a background driving voltage in each testing channel, wherein the background driving voltage is used for offsetting the corresponding first tested voltage; configuring corresponding testing channels according to the background driving voltage; and measuring the tested chip by using the configured testing channels, and reading the static working current of the tested chip at the moment. According to the invention, the leakage current of each testing channel can be significantly reduced, and the precision of chip measurement is improved.
Description
technical field [0001] The invention relates to the technical field of chip testing, in particular to a chip testing method, a testing machine and a storage medium. Background technique [0002] In the chip test, there is a special current measurement item of the power pin in low power consumption mode. With the higher demand of chip terminal application equipment for low power consumption performance during standby, the low power consumption working state current of the chip is getting smaller and smaller, from the previous microampere (µA) level to nanoampere (nA) level level, even to the pico-anne (pA) level. The requirements for the measurement accuracy and stability of the very small current of the integrated circuit testing machine are also getting higher and higher. [0003] The static working current of the chip is usually composed of two parts. One is the actual internal power consumption of the chip in low-power standby mode, which is usually a stable small curr...
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