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Semiconductor structure and preparation method thereof

A semiconductor and contact structure technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems affecting the conduction resistance of the bit line structure

Pending Publication Date: 2021-10-19
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The mask pattern structure of a typical bit line contact hole is formed by stacking patterned mask layers composed of multiple layers of different materials. The deposition rate on the mask layer made of materials is different, and the bit line contact material will be "sealed" in advance in the middle of the bit line contact hole to form a bit line contact material layer with holes or gaps, and then a bit line contact material layer with holes or gaps will be obtained. Line contact structure, and the existence of voids or gaps will affect the resistance of the bit line contact structure, and then affect the conduction resistance of the bit line structure, how to eliminate the void or gap in the bit line contact structure has become an urgent problem to be solved

Method used

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  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof

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Embodiment Construction

[0051] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. A preferred embodiment of the application is shown in the drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

[0053]It will be understood that when an element or layer is referred to as being "on," "adjace...

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Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The method comprises the steps that: a substrate is provided, wherein a shallow trench isolation structure is formed in the substrate and is used for isolating a plurality of active regions which are arranged at intervals in the substrate; a patterned mask structure is formed on the substrate, wherein the patterned mask structure comprises a first mask layer and a second mask layer which are sequentially stacked upwards from the substrate; an etching process is carried out so as to enable the side wall of the first mask layer to be concave inwards; the substrate is patterned based on the patterned mask structure so as to form a bit line contact hole exposing the active region in the substrate; and a bit line contact structure is formed in the bit line contact hole. When a bit line contact material forming the bit line contact structure is formed, the recessed side wall of the first mask layer delays the 'sealing' time of the bit line contact material at the position of the first mask layer, so that no cavity or gap is formed in the bit line contact material (the bit line contact structure).

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof. Background technique [0002] The mask pattern structure of a typical bit line contact hole is formed by stacking patterned mask layers composed of multiple layers of different materials. When depositing a bit line contact material layer in a bit line contact hole, the bit line contact material is different The deposition rate on the mask layer made of materials is different, and the bit line contact material will be "sealed" in advance in the middle of the bit line contact hole to form a bit line contact material layer with holes or gaps, and then a bit line contact material layer with holes or gaps will be obtained. Line contact structure, and the existence of voids or gaps will affect the resistance of the bit line contact structure, and then affect the conduction resistance of the bit line struc...

Claims

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Application Information

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IPC IPC(8): H01L21/8242H01L27/108
CPCH10B12/34H10B12/485
Inventor 刘浩
Owner CHANGXIN MEMORY TECH INC