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Memory circuit system, device and writing method

A memory circuit and storage circuit technology, applied in the field of memory, can solve the problems of slow writing speed, cumbersome writing process, low utilization rate of EEPROM storage space, etc., and achieve the effect of improving utilization rate and writing speed.

Active Publication Date: 2021-12-14
ZHEJIANG GEOFORCECHIP TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, the overall writing process of EEPROM is relatively cumbersome, and the writing speed is slow, which will reduce the utilization rate of EEPROM storage space

Method used

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  • Memory circuit system, device and writing method
  • Memory circuit system, device and writing method
  • Memory circuit system, device and writing method

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Embodiment Construction

[0059] Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided for thorough understanding of the application and to fully convey the scope of the application to those skilled in the art.

[0060] It should be noted that, unless otherwise specified, technical terms or scientific terms used in this application shall have the usual meanings understood by those skilled in the art to which this application belongs.

[0061] A memory circuit system, device, and writing method according to the embodiments of the present application are described below with reference to the accompanying drawings. The memory can be, but not limited to, the a...

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Abstract

The application proposes a memory circuit system, device and writing method. The memory circuit system includes: a plurality of storage circuits arranged in a matrix, and the input terminals of each storage circuit are respectively connected to word lines, bit lines, and control gate lines. And chip select signal line; write amplifier circuit, its input end is connected with decoder circuit, output end is respectively connected with bit line and chip select signal line; control line generation circuit, its input end is connected with decoder circuit, output end respectively connected to the word line and the control gate line; the decoder circuit records and transmits address information to the write amplifier circuit or the control line generation circuit; the integrated control circuit transmits the control signal to the write amplifier circuit and the control line generation circuit, and decodes The memory circuit jointly controls the word line, the bit line, the control gate line and the chip selection signal line, so that the storage circuit performs multiple writing operations in succession. The application can be directly written without erasing before writing, thereby improving the writing speed and the utilization rate of the storage space of the EEPROM.

Description

technical field [0001] The present application belongs to the technical field of memory, and in particular relates to a memory circuit system, device and writing method. Background technique [0002] EEPROM (Electrically Erasable Programmable read only memory) usually refers to an electrically erasable programmable read-only memory. Because of its user-changeable, electrical signal erasable and programmable, and data not lost after power-off, it is often used in chip to store a large amount of important data. During the normal working process of the chip, EEPROM will be read, erased and written multiple times, and the length of time for reading, erasing or writing EEPROM will affect the length of time for the chip to execute instructions. [0003] At present, most of the writing process of existing EEPROM is: before each writing, first read out the data of the whole page, and write it into the cache, and then perform page erasing (byte erasing or block erasing can also be p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10G11C16/30
CPCG11C16/10G11C16/30
Inventor 不公告发明人
Owner ZHEJIANG GEOFORCECHIP TECH CO LTD