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Wafer-level packaging method and wafer-level packaging structure

A wafer-level packaging and wafer technology, which is applied in the field of wafer-level packaging methods and wafer-level packaging structures, can solve problems such as inability to cut the edge of the wafer, strike pins, and difficulty in taking chips, so as to prevent water vapor and increase availability. Quantity effect

Pending Publication Date: 2021-11-02
SEMICON MFG ELECTRONICS (SHAOXING) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the existing wafer-level packaging technology is prone to the problem that the edge of the wafer cannot be cut during dicing, which in turn leads to problems such as hitting the needle and taking out the chip during the wafer needle test (CP test).

Method used

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  • Wafer-level packaging method and wafer-level packaging structure
  • Wafer-level packaging method and wafer-level packaging structure
  • Wafer-level packaging method and wafer-level packaging structure

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Embodiment Construction

[0033] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention. It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on" or...

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Abstract

The invention provides a wafer-level packaging method and a wafer-level packaging structure, and the method comprises the steps: enabling the inner edge of a first metal sealing ring of a lower-layer wafer to extend inwards for 1mm or more than the inner edge of a second metal sealing ring of an upper-layer wafer, so the upper and lower layers of wafers are provided with enough process windows to ensure metal bonding between the first metal sealing ring and the second metal sealing ring; reserving the second metal sealing ring with the required distance when the upper layer of wafer is trimmed, so the sealing effect of the wafer-level packaging structure after bonding and trimming can be ensured, the wafer-level packaging structure prevents water vapor, scribing liquid and the like from entering, solves the problem that the edge of the wafer-level packaging structure cannot be scribed open during subsequent scribing, does not need to increase the technological process, and can increase the available number of effective chips.

Description

technical field [0001] The invention relates to the technical field of wafer packaging, in particular to a wafer-level packaging method and a wafer-level packaging structure. Background technique [0002] Wafer-level packaging of devices such as MEMS (Micro-Electro-Mechanical Systems, Micro-Electro-Mechanical Systems), usually provides a lower wafer with metal bonding pads and an upper wafer with metal bonding pads, and the lower wafer and the upper wafer The metal bonding pads of the upper wafer are butted together for metal bonding, and the edges of the lower wafer and the upper wafer are bonded together by a frame glue or a metal sealing ring to prevent the subsequent scribing process from occurring. Due to the unsealed edge of the wafer, water vapor and dicing fluid enter the wafer and cause chip failure. After that, the dicing process is performed to form several independent chips (die). [0003] However, the existing wafer-level packaging technology is prone to the pr...

Claims

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Application Information

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IPC IPC(8): B81C1/00B81B7/00B81B7/02
CPCB81B7/02B81B7/007B81C1/00301B81C2203/01
Inventor 王红海
Owner SEMICON MFG ELECTRONICS (SHAOXING) CORP
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