Static random access memory unit structure and static random access memory

Abstract

The invention discloses a static random access memory unit structure. The static random access memory unit structure comprises a first phase inverter, a second phase inverter, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube, wherein the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the input end of the first phase inverter; the source electrode or the drain electrode of the third NMOS tube is connected with the output end of the first phase inverter; the source electrode or the drain electrode of the fourth NMOS tube is connected with the output end of the second phase inverter; and the grid electrode of the fifth NMOS tube is connected with the output end of the second phase inverter. The static random access memory unit structure provided by the invention is provided with the gate end reading transistor, so that the read operation and the write operation of the static random access memory unit structure can be completely decoupled, the interference on stored data during the read operation can be avoided, the read operation capability is improved, and a noise margin window is greatly improved; therefore, the static random access memory unit structure is more suitable for low-voltage and low-power-consumption application scenarios.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a static random access memory unit structure and a static random access memory. Background technique [0002] Static random access memory (SRAM) is an integral part of integrated circuits, and is mainly used for short-term data storage and data calculation. Generally speaking, SRAM is the circuit module with the most stringent design rules, the most densely arranged components, the fastest operating speed and the highest operating power consumption in the chip circuit. Traditional SRAM storage uses a 6T (6 transistors) structure or an 8T (8 transistors) structure to store 1-bit or 2-bit data. [0003] The development of microelectronics technology puts forward the requirements of higher density, higher operating speed and lower power consumption for SRAM, that is, the requirement of high energy efficiency. In the existing solution, by reducing the operatin...

AI Technical Summary

Problems solved by technology

However, reducing the operating voltage brings many challenges to the traditional 6T / 8T structure. The more serious challenge is that the noise margin window (SNM) of the memory cell is reduced, making the information stored in the SRAM cell easily disturbed and lost.

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