Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps that a substrate which comprises a substrate body and a stacking structure which are stacked in sequence is provied; a second sacrificial layer is formed on the exposed surface, away from the substrate, of each first sacrificial layer, a plurality of preparation steps are obtained, each second sacrificial layer comprises a plurality of stacked second sub-sacrificial layers, and in any two adjacent second sub-sacrificial layers, the doping concentration of the first second sub-sacrificial layer is lower than that of the second second sub-sacrificial layer; a dielectric material is deposited on the exposed surface of the substrate and the exposed surface of each preparation step; the material of the first sacrificial layer and the material of the predetermined part of the second sacrificial layer in each preparation step are respectively replaced with conductive materials to form a plurality of conductive layers, and the replaced preparation steps are steps; and the substrate on which the plurality of steps are formed is etched, so that the conductive layer of each step is exposed, and a plurality of grooves are formed. The method ensures that the manufacturing yield is high.

Description

Technical field [0001] The present application relates to the field of semiconductors, and in particular, relates to a method for manufacturing a semiconductor structure and a semiconductor structure. Background technique [0002] 3D NAND memory each of a WL (word line, word line) require CT (contact, the contact hole) connecting the WL out to Metal (metal) end, to a single WL, i.e. a single memory unit provides a voltage to achieve control memory. The present process generally is formed in a stepped approach the bulk region, an etching stop layer by thickening, reducing the risk of wear of the etching time. But the process, because of the different position of WL which is not the same, from the top film (top layer) of different height, in this case, when the etching CT need to ensure access to the WL below while also WL is not guaranteed above the penetrated, therefore, the thickness of each layer of the etching stop layer is difficult to control, resulting in a low process yiel...

AI Technical Summary

Problems solved by technology

[0004] The main purpose of the present application is to provide a method for manufacturing a semiconductor structure and a semiconductor structure to solve the problem that the thickness of the etch stop layer is difficult to control in the word line connection process in the prior art, resulting in a low process yield.

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