Self-adaptive reconfigurable processing array and master control interaction method and device

An interaction method and technology of an interaction device, applied in the field of an adaptive reconfigurable processing array and a main control interaction method and device, can solve problems such as wasting clock cycles and increasing time overhead, and achieve reduced coupling, shortened execution time, The effect of increasing computing power and computing performance

An interaction method and technology of an interaction device, applied in the field of an adaptive reconfigurable processing array and a main control interaction method and device, can solve problems such as wasting clock cycles and increasing time overhead, and achieve reduced coupling, shortened execution time, The effect of increasing computing power and computing performance

CN113792009APending Publication Date: 2021-12-14TSINGHUA UNIV
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  • Self-adaptive reconfigurable processing array and master control interaction method and device
  • Self-adaptive reconfigurable processing array and master control interaction method and device
  • Self-adaptive reconfigurable processing array and master control interaction method and device

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Embodiment Construction

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

[0020] figure 1 It is the architecture diagram of the reconfigurable processor block RPU (reconfigurable processor unit), such as figure 1 Shown is an architecture diagram of a reconfigurable processor block RPU (reconfigurable processor unit). An RPU has four PEAs (processing element array, processing unit array). The main control RISCV (RISCV processor) interacts with the PEA through the coprocessor interface. The Data Cache (data cache) stores data, and sends the data to the shared memory module (share memory) on the PEA array through the AHB bus. The Context C...

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Abstract

The invention discloses a self-adaptive reconfigurable processing array and master control interaction method and device. The device comprises a control type processing unit which is arranged on a reconfigurable processing array and is used for replacing a master control to read and write a global register GR in a coprocessor interface, so as to realize carrying of data and execution of the array. According to the method, the coupling degree of the array and the master control is greatly reduced, the application execution time is shortened, and the computing power and the computing performance are greatly improved, so that the requirement for the application computing performance is met, and the method is very suitable for being applied to hardware acceleration design for data-intensive and computing-intensive applications.

Description

technical field [0001] The invention relates to the technical field of large-scale integrated circuits, in particular to an adaptive reconfigurable processing array and a master control interaction method and device. Background technique [0002] This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section. [0003] The coprocessor interface module is a bridge between the main control and the reconfigurable processing array. In addition to reading and writing the shared global registers on the reconfigurable processing array, the coprocessor interface also has 10 reconfigurable processing array-oriented functions. Controlled global registers, these 10 registers are not visible to the processing elements in the reconfigurable processing array. The coprocessor interface module generates enable signals by analyzing the values ​​o...

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Application Information

Patent Timeline
14 Dec 2021
Publication
CN113792009A
IPC
G06F15/78
CPC
G06F15/7839; G06F15/7871
Inventors
尹首一; 钟鸣