Chip failure mode determination method and terminal

Abstract

The invention discloses a chip failure mode determination method and a terminal. The method comprises the following steps: acquiring failure bits of a chip under a plurality of test voltages; carrying out failure mode operation on the obtained failure bits, and obtaining at least one failure bit group and a failure mode of each failure bit group, wherein the failure bit group comprises at least one failure bit under the test voltage; and determining the failure mode of the failure bits in the failure bit group based on the failure mode of the failure bit group. Through the scheme of the invention, the accuracy of chip failure analysis can be improved.

Description

technical field [0001] The invention relates to the technical field of chip manufacturing and testing, in particular to a method for determining a failure mode of a chip and a terminal. Background technique [0002] In the era of big data, the demand for memory chips has exploded. At present, memory chips can be divided into many types according to different storage mechanisms, such as Static Random-Access Memory (SRAM for short), memory using NAND technology, memory using NOR technology, and Read-Only Memory (Read-Only Memory). , referred to as ROM) and so on. Taking SRAM as an example, SRAM is widely used in the field of logic chips, and most of the embedded memories of logic products are realized by SRAM. In addition, SRAM is used as a standard R&D tool for new process nodes by logic chip manufacturing plants due to its convenient failure analysis, consistency of manufacturing process and logic chips. In other words, SRAM will be used as a tool "product" for the develo...

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Problems solved by technology

[0005] However, there are flaws in the failure mode classification and hard / soft failure discrimination logic used in the prior art, resulting in low accuracy of failure analysis for chips

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