Deep learning training method based on Tensorflow framework

Abstract

The invention provides a deep learning training method based on a Tensorflow framework. The deep learning training method comprises the steps of receiving a deep learning training request; virtualizing an FPGA board card corresponding to the deep learning training request into a local FPGA node; registering a local FPGA node as a VFPGA device corresponding to the Tensorflow framework; configuring a forward operator and a reverse operator of the VFPGA equipment, and compiling the forward operator and the reverse operator to obtain a bit file of the FPGA; programming the bit file to a local FPGA node, and generating an FPGA device corresponding to the local FPGA node; and executing deep learning training by utilizing the FPGA equipment. According to the invention, the communication time delay is reduced, so that the deep learning training efficiency is improved. The invention also provides a deep learning training system based on the Tensorflow framework, an FPGA board card, a computer readable storage medium and electronic equipment, which have the above beneficial effects.

Description

technical field [0001] This application relates to the field of big data, and in particular to a deep learning training method, system, FPGA board, computer-readable storage medium and electronic equipment based on the Tensorflow framework. Background technique [0002] Tensorflow is one of the most widely used deep learning training frameworks, and most companies use tensorflow as their preferred training framework. Therefore, tensorflow has been supported by many chip manufacturers, such as intel's CPU, AMD's CPU and APU, nvidia's GPU, intel and silinx and other leading FPGA chip manufacturers have implemented FPGA support for tensorflow reasoning. However, when using a host in PCIE mode for model training, it is limited by the number of FPGA card slots in the server, which will become a bottleneck in large-scale deployment. At the same time, since the communication between multiple FPGA boards based on the PCIE mode needs to be carried out by the CPU, the communication t...

AI Technical Summary

Problems solved by technology

However, when using a host in PCIE mode for model training, it is limited by the number of FGPA card slots in the server, which will become a bottleneck in large-scale deployment

At the same time, since the communication between multiple FPGA boards based on the PCIE mode needs to be carried out by the CPU, the communication time is relatively long, that is, the communication is limited

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