Heterogeneous multi-core microprocessor based on multi-layer bus

Abstract

The invention discloses a heterogeneous multi-core microprocessor based on a multilayer bus. The heterogeneous multi-core microprocessor comprises a plurality of processing cores for uniform addressing, wherein the plurality of processing cores have different pipeline structures; the plurality of processing cores are connected through an AXI bus with bridge connection; the AXI bus with bridge connection is connected with a notepaper type memory; data packets are sent and read between every two processing cores through a scratch pad memory; a data packet head address and a data packet length are directly sent between every two processing cores so as to assist in completing the transmission of a data packet between the two processing cores; and the AXI bus with bridging is also connected with a peripheral interface, and the processing cores perform access control on external equipment through the peripheral interface. According to the heterogeneous multi-core microprocessor based on themulti-layer bus, disclosed by the invention, the communication delay can be reduced.

Description

technical field [0001] The invention belongs to the technical field of multi-core microprocessors, in particular to a multi-layer bus-based heterogeneous multi-core microprocessor. Background technique [0002] At present, the core structures of multi-core microprocessors mainly include two types: homogeneous and heterogeneous. The isomorphic structure adopts a symmetrical design, the principle is simple, and it is easier to implement in hardware. Compared with the homogeneous structure, the advantage of heterogeneity is to optimize the internal structure of the processor by organizing cores with different characteristics. Each core can optimize the performance of the processor according to different needs, and can effectively reduce power consumption. Since each processor core in a heterogeneous multi-core microprocessor executes completely different instruction streams, the processor's instruction operations at the same time are basically different, and its busy condition...

AI Technical Summary

Problems solved by technology

The advantages of the general bus sharing structure are simple structure and high communication speed. The disadvantage is that the bus-based structure has poor scalability and the effect of reducing communication delay is not good. The advantage of crossbar interconnection and on-chip network structure is that it can be expanded. Good performance, data bandwidth is guaranteed, but the hardware structure is complex, and the software changes greatly, generally not suitable for microprocessors

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