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Semiconductor packaging structure

A packaging structure and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problem of unable to prevent the delamination and cracks of the underfill, and avoid the delamination and cracks of the underfill. Effect

Pending Publication Date: 2022-02-08
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this approach does not prevent underfill delamination (delam) and cracking issues

Method used

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  • Semiconductor packaging structure
  • Semiconductor packaging structure
  • Semiconductor packaging structure

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Embodiment Construction

[0037] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first part over or on a second part may include embodiments in which the first part and the second part are in direct contact, and may also include forming additional parts between the first part and the second part Embodiments such that the first part and the second part may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for brevity and clarity only and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0038] Figure 2A It is a schema...

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Abstract

The invention relates to a semiconductor packaging structure. The semiconductor packaging structure comprises a circuit layer; a first chip and a second chip which are located above the circuit layer; and a strengthening structure which is located under the first chip and the second chip, and the strengthening structure abuts against the lower surface of the first chip, the lower surface of the second chip and the upper surface of the circuit layer.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and more particularly, to a semiconductor packaging structure. Background technique [0002] In the existing semiconductor packaging structure, such as figure 1 The FoCoS (Fan-Out Chip-on-Substrate) package structure shown, such as the first chip 12 of ASIC (Application Specific Integrated Circuit) and the first chip 12 such as HBM (High Bandwidth Memory, high bandwidth memory) The second chip 14 is located on a redistribution line (RDL) layer 24 on the substrate 22 . The lower portions of the first chip 12 and the second chip 14 are surrounded by an underfill 30 . Because of the mismatch of CTE (coefficient of thermal expansion, coefficient of thermal expansion) between materials, warpage (Warpage) will occur during thermal cycling. Since the overall package structure cannot directly release the stress caused by warpage, the under-fill (Under-Fill) is prone to cracks 29 at the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/00H01L23/16H01L23/538
CPCH01L23/3128H01L23/562H01L23/16H01L23/5386
Inventor 吕文隆
Owner ADVANCED SEMICON ENG INC