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Method for inhibiting writing fluctuation of ferroelectric transistor FeFET

A ferroelectric transistor and write operation technology, which is applied to digital memory information, instruments, biological neural network models, etc., can solve problems such as the disappearance of storage windows, the decrease of neural network accuracy, and the sacrifice of dynamic range of units, so as to improve accuracy and reduce conductance Fluctuation effect

Pending Publication Date: 2022-02-25
PEKING UNIV
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  • Abstract
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  • Application Information

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Problems solved by technology

However, due to the non-uniform distribution of ferroelectric domains in the ferroelectric layer of FeFET and the random polarization flipping characteristics, FeFET has a high write fluctuation problem, which will lead to the disappearance of its storage window and the decrease of the accuracy of the neural network formed.
Recently, some work proposed to use a current-limiting structure composed of a FeFET and a resistor to suppress the fluctuation of the binary synaptic weight unit, but at the expense of the dynamic range of the unit
Some studies have proposed to use write-and-verify to suppress the fluctuation of FeFET, but it requires complex timing control circuit and high programming power consumption

Method used

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  • Method for inhibiting writing fluctuation of ferroelectric transistor FeFET

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Embodiment Construction

[0019] The present invention will be further elaborated below through specific embodiments in conjunction with the accompanying drawings.

[0020] This embodiment uses Hf 0.5 Zr 0.5 o 2 The ferroelectric transistor FeFET of ferroelectric material, at this time, the spontaneous polarization of ferroelectric material will induce additional charges on the gate oxide layer of MOSFET, resulting in a change in the channel conductance of the device. The charge induced by the ferroelectric polarization charge on the gate oxide layer of the MOSFET can also be equivalent to an additional gate voltage, which can be reflected on the entire FeFET as a change in the channel conductance of the device.

[0021] Such as figure 1 As shown, the present embodiment is a method for suppressing the write fluctuation of the ferroelectric transistor FeFET, including the ferroelectric transistor FeFET, the NMOS (N1) of the write operation path, and the NMOS (N2) of the read operation path; wherein, ...

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Abstract

The invention provides a method for inhibiting writing fluctuation of a ferroelectric transistor FeFET, and belongs to the field of neural network accelerators. A FeFET source end voltage negative feedback mechanism is utilized to be connected with an NMOS (N1) of a write operation channel and an NMOS (N2) of a read operation channel; the gate end of the FeFET is used as a programming (or erasing) port, the drain end of the FeFET is connected to a power supply voltage VDD, and the source end of the FeFET is connected with the drain ends of the N1 and the N2; the source ends of the N1 and the N2 are connected to the GND; during read operation, N1 is turned off, N2 is turned on, and FeFET channel conductance is extracted; during writing operation, the gate voltage of the N1 is fixed, the N2 is turned off, the FeFET and the N1 form a source following negative feedback writing operation path, the VGS of the FeFET changes dynamically in a self-adaptive mode along with polarization overturning, and writing operation fluctuation of the FeFET is restrained. According to the invention, hardware overhead and energy consumption are reduced, and realization of a high-precision low-power-consumption neural network accelerator chip is facilitated.

Description

technical field [0001] The invention relates to the physical realization of the synaptic weight unit in the neural network accelerator, in particular to a method for suppressing the write fluctuation of the ferroelectric transistor FeFET. Background technique [0002] With the vigorous development of information technology, human society has entered the era of "data explosion", and the annual exponential growth of data volume has brought unprecedented pressure on data processing and calculation. Due to the characteristics of the traditional von Neumann computing architecture, which separates storage and computing, the transmission of data between the storage unit and the computing unit will cause a lot of waste of power consumption and energy consumption. In today's information society and even the intelligent society, there is a huge amount of data In this context, this problem will become more and more serious. Inspired by the computing model of the human brain, the resea...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/22G11C16/34G06N3/063
CPCG11C11/2275G11C16/34G06N3/063
Inventor 黄如罗金徐伟凯黄芊芊
Owner PEKING UNIV
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