Storage renaming implementation method, processor and computer equipment

An implementation method and register renaming technology, which are applied in computing, register devices, and electrical digital data processing, etc., can solve storage problems that plague processors, such as performance improvement, large storage resource occupation, and power consumption, etc., to improve processor performance. Performance, reduced resource usage, and reduced power consumption

Pending Publication Date: 2022-03-01
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] Storage issues have always been a problem that has plagued processor performance improvements
However, the implementation method of this storage renaming technology has the following problems: (1) the data transmission between the Store and the Load is carried out through the value file, and each item of the value file is at least 64 bits, and the storage resou

Method used

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  • Storage renaming implementation method, processor and computer equipment

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Embodiment Construction

[0020] see figure 1 The implementation method of storage renaming in this embodiment includes the following steps after instruction decoding and before register renaming:

[0021] 1) Judging the instruction type of the decoded instruction and whether storage renaming is required;

[0022] 2) If storage renaming is required and the instruction type is a Store instruction, write the source register number of the Store instruction into the value file; if storage renaming is required and the instruction type is a Load instruction, then the Load is judged by storage dependency prediction Whether there is a dependency between the instruction and the previous Store instruction, and if there is a dependency with the previous Store instruction, the value transfer between the Load instruction and the Store instruction it depends on is performed through register transfer.

[0023] The method of this embodiment realizes the optimization of the content stored in the value file (value file...

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Abstract

The invention discloses a storage renaming implementation method, a processor and computer equipment. The method comprises the following steps: after instruction decoding and before register renaming, judging the instruction type of an instruction obtained by decoding and judging whether storage renaming needs to be performed or not; if storage renaming needs to be carried out and the instruction type is a Store instruction, writing a source register number of the Store instruction into a value file; if storage renaming needs to be carried out and the instruction type is a Load instruction, whether the Load instruction depends on a previous Store instruction or not is judged through storage dependency prediction, and if the Load instruction depends on the previous Store instruction, quota value transmission between the Load instruction and the dependent Store instruction is carried out in a register transmission mode. According to the invention, resource occupation caused by implementation can be reduced, execution power consumption is reduced, and processor performance is further improved.

Description

technical field [0001] The invention relates to the field of processor architecture, in particular to a storage renaming implementation method, processor and computer equipment. Background technique [0002] Storage issues have always been a problem that has plagued processor performance improvements. When storing data, the dependency between the load (Load) and store (Store) instructions needs to be judged by accessing the stored address. That is to say, if the address of the Store instruction overlaps with the address of the subsequent Load instruction, then the subsequent Load instruction needs to obtain data from the data stored in the Store instruction. This kind of data dependence needs to wait for both Store and Load to be executed before the dependency relationship can be judged by comparing addresses. [0003] A storage renaming technology is disclosed in the prior art (Tyson, G.S., Austin, T.M. Memory Renaming: Fast, Early and Accurate Processing of Memory Commun...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/3004G06F9/30098G06F9/3867
Inventor 郑重邓全郭辉黄立波王俊辉孙彩霞倪晓强郭维隋兵才王永文
Owner NAT UNIV OF DEFENSE TECH
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