Method for accelerating adaptive reconfigurable processing unit array system based on network

A processing unit and self-adaptive technology, applied in the multi-core field, can solve problems such as performance and efficiency degradation, performance and efficiency degradation, reconfigurable resource idle waste, etc., to achieve the effect of improving performance, improving performance and efficiency

Inactive Publication Date: 2009-08-12
ZHEJIANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] But an isolated node does not have enough power and flexibility to handle some applications
[0007] Insufficient reconfigurable resources: When the application needs more reconfigurable resources than an isolated node has, in this case, some requests of the application must be suspended until the occupied reconfigurable resources are Released and reconfigured before proceeding, which reduces performance and efficiency
[0008] Waste of reconfigurable resources: Whe

Method used

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  • Method for accelerating adaptive reconfigurable processing unit array system based on network
  • Method for accelerating adaptive reconfigurable processing unit array system based on network
  • Method for accelerating adaptive reconfigurable processing unit array system based on network

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Embodiment Construction

[0043] The relevant symbolic interpretations are involved in the method:

[0044] C1: Can run on reconfigurable devices;

[0045] C2: The general processor of the local node is idle;

[0046] C3: The reconfigurable device of the local node is idle;

[0047] C4: There is a neighbor node reconfigurable device idle;

[0048] The specific implementation process of the network-based adaptive reconfigurable processing unit array acceleration system is as follows.

[0049] Step 1: Tasking of the original program:

[0050] 1: The system divides a program into two sets {{A}, {B}} of independently runnable tasks. Set A represents tasks that cannot be run on reconfigurable devices, and set B represents tasks that cannot be run on reconfigurable devices. Tasks running on the device.

[0051] 2: Generate a dependency table between tasks according to the dependencies between tasks.

[0052] Step 2: Build a network-based adaptive reconfigurable processing unit array:

[0053] like fi...

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Abstract

The invention discloses a method for accelerating a network-based adaptive reconfiguring processing unit array system. According to the method, an adaptive reconfiguring processing unit network is formed by computing nodes formed by general processors and reconfiguring equipment. A program needing to be executed is divided into a collection of tasks which can operate independently; and each task in the collection of the tasks is allocated through the adaptive reconfiguring processing unit network to find a suitable computing resource to be executed and can be reconfigured by making use of the characteristics of high efficiency and flexibility of the reconfiguring equipment, so that the function of the reconfiguring equipment can meet the demands of different tasks. Under the action of the adaptive reconfiguring processing unit network, the network-based adaptive reconfiguring processing unit array system can intelligently allocate the tasks according to the condition of nodes in the network and primarily allocates the tasks to other nodes with idle computing resources so as to reduce the time of executing the program, improve the utilization rate of the reconfiguring equipment and achieve the purpose of accelerating the program.

Description

technical field [0001] The present invention relates to the multi-core technical field and the reconfigurable technical field, in particular to an implementation method of a reconfigurable multi-core accelerated program execution based on network communication. Background technique [0002] With the continuous improvement of the computer manufacturing technology level, the VLSI technology has made great progress, and the multi-core technology has become the current mainstream processor technology. However, with the increasing number of processor cores, how to improve the utilization of these cores has become a difficult problem. [0003] Since the parallelism of general applications is not high, it is generally considered that after the number of general-purpose cores of a processor exceeds 16, it is difficult to increase the number of general-purpose processing cores to improve performance. [0004] In a heterogeneous multi-core processor, some special-purpose cores custom...

Claims

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Application Information

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IPC IPC(8): H04L29/08G06F9/46
Inventor 胡威吴斌斌冯德贵王超曹满马建良陈度王罡施青松陈天洲
Owner ZHEJIANG UNIV
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