Method for programming memory device
A memory and row storage technology, applied in the field of operating memory devices, can solve the problems of high time overhead and power consumption, and reducing the programming performance of memory devices, etc.
Pending Publication Date: 2022-03-01
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
Since the programming pulse time is usually much shorter than the verification operation time in the programming cycle, the time overhead and power consumption brought by the verification operation are often very large, thereby also reducing the programming performance of the memory device.
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Embodiment Construction
[0016] figure 1 A schematic circuit diagram of an exemplary memory device is shown. Such as figure 1 As shown, the memory device may be a NAND-type flash memory whose memory array provides memory cells 106 in the form of NAND strings 108 . The memory device includes a memory cell array having a plurality of rows of memory cells 106 , and a plurality of word lines 118 respectively coupled to the rows of memory cells 106 . According to some implementations, the NAND string 108 may be organized into a plurality of memory blocks 104 , and each memory block 104 may have a common source line 114 . NAND strings 108 in the same memory block 104 are coupled to, for example, ground through a common source line 114 . According to some implementations, each NAND string 108 is coupled to a respective bit line 116 from which data can be read via an output bus (not shown). The memory cells 106 of adjacent NAND strings 108 may be coupled by a word line 118, which is used to select which r...
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Disclosed is a memory device including: a memory cell array having a plurality of rows of memory cells; a plurality of word lines respectively coupled to the plurality of rows of memory cells; wherein the memory device is configured to perform a programming operation on a target memory cell in the plurality of rows of memory cells, and during the programming operation, a programming voltage is applied to a selected word line corresponding to the row where the target memory cell is located so as to program the target memory cell to a target programming state; applying a predetermined voltage to the selected word line to suppress voltage change caused by capacitive coupling between an unselected word line adjacent to the selected word line and the selected word line; and applying a verification voltage to the selected word line to execute a verification operation to verify whether a threshold voltage of the target memory cell is greater than a target threshold voltage corresponding to the target programming state based on the predetermined voltage.
Description
technical field [0001] The present invention relates to a method for operating a memory device, and more particularly, to a method for operating a memory device with multi-level cells. Background technique [0002] When programming solid-state drive (SSD) memory cells, especially for multi-level cells of NAND flash memory, the programming pulse is usually followed by several verification operations to form target programming states with different threshold voltages. Since the programming pulse time is usually much shorter than the verification operation time in the programming cycle, the time overhead and power consumption brought by the verification operation are often very large, thereby reducing the programming performance of the memory device. [0003] Therefore, there is a need for a memory device programming method capable of reducing the time overhead of verify operations, thereby further improving programming performance. Contents of the invention [0004] Accordi...
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IPC IPC(8): G11C16/08G11C16/10G11C16/24
CPCG11C16/08G11C16/10G11C16/24G11C16/3459G11C16/0483G11C11/5628G11C16/3427G11C16/32G11C16/102
Inventor 王瑜
Owner YANGTZE MEMORY TECH CO LTD