Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, which are used for reducing the design difficulty and the preparation cost of the semiconductor structure. The semiconductor structure includes a plurality of semiconductor devices. The semiconductor device includes a substrate and a reference pattern. In two adjacent semiconductor devices, the semiconductor device located on the lower layer is the first semiconductor device, and the semiconductor device located on the upper layer is the second semiconductor device. The light transmittance of at least the part, corresponding to the reference pattern of the first semiconductor device, in the substrate of the second semiconductor device is smaller than or equal to the preset light transmittance. The preset light transmittance is the maximum light transmittance of the part, corresponding to the reference pattern of the first semiconductor device, in the substrate of the second semiconductor device under the condition that the reference pattern of the first semiconductor device cannot be recognized from one side, far away from the first semiconductor device, of the second semiconductor device. Orthographic projections of the reference pattern of the second semiconductor device and the reference pattern of the first semiconductor device are at least partially overlapped. The semiconductor structure is used for realizing data reading and writing operations.

Description

technical field [0001] The invention relates to the technical field of semiconductor chips, in particular to a semiconductor structure and a preparation method thereof. Background technique [0002] As the feature size of the memory cell approaches the lower limit of the process, the planar process and manufacturing technology becomes challenging and expensive, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. [0003] In order to overcome the limitations brought by 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases storage density by three-dimensionally arranging memory cells on a substrate. Contents of the invention [0004] Embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof, which are used to reduce the area occupied by an alignment pattern in a semiconductor device, and reduce design difficul...

AI Technical Summary

Problems solved by technology

[0002] As the feature size of the memory cell approaches the lower limit of the process, the planar process and manufacturing technology becomes challenging and expensive, which causes the storage density of 2D or planar NAND flash to approach the upper limit

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