Packaging method and packaging structure of fan-out stacked chip

Abstract

The invention provides a fan-out stacked chip packaging method and packaging structure, and the method comprises the steps: enabling a first chip to be fixed in a groove body of a dummy chip, and enabling the first chip and the dummy chip to be provided with a plurality of conductive through holes; performing thermocompression bonding on the second chip with the dummy chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip falls on the inner side of the dummy chip; forming a first plastic package layer, wherein the first plastic package layer wraps the second chip; forming a second plastic package layer, wherein the second plastic package layer wraps the first chip, the dummy chip, the second chip and the first plastic package layer; and forming a rewiring layer on the surfaces, deviating from the second chip, of the dummy chip and the first chip, wherein the rewiring layer is electrically connected with the first chip through the conductive through hole. According to the invention, the first chip and the second chip are respectively subjected to wafer expansion through the dummy wafer and the first plastic packaging layer, and then wafer-level thermocompression bonding is carried out, so that high-density interconnection is realized, and meanwhile, the production efficiency is improved. The packaging size is reduced through the conductive through holes and the fan-out rewiring technology, and ultra-thin multi-layer high-density stacked packaging is achieved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a fan-out stacked chip packaging method and packaging structure. Background technique [0002] The size of electronic products is getting smaller and smaller, and their functions are getting stronger. Subsequently, semiconductor packages are required to be thinner and thinner, and the interconnection density is higher. Traditional packaging cannot meet future demands. figure 1 It is a typical traditional multi-layer chip packaging structure. Chips 1 and 2 are vertically stacked on a substrate 6 through patch films 3 and 4 , and chips 1 and 2 are connected to the substrate 6 through gold wires 5 . Chips 1, 2 and gold wire 5 are protected by plastic encapsulant 7. The entire package is connected to the outside world through solder balls 8 . In the current packaging, due to the limitation of the height of the molding of the gold wire and the limitatio...

AI Technical Summary

Problems solved by technology

In the current packaging, due to the height limitation of the molding of the gold wire and the limitation of the protection distance from the molding compound to the gold wire, the height from the molding compound to the surface of the chip 2 is strictly limited and cannot be continuously reduced.

At the same time, the substrate process is extremely difficult to produce ultra-thin substrates due to material limitations and substrate strength limitations, which limit the application of traditional packaging in ultra-thin multi-layer packaging.

And whether it is traditional wire bonding connection or reverse soldering connection, the pad spacing is more than 30um, and it is extremely difficult to continue to shrink

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