Integrated circuit yield estimation method and memory
An integrated circuit and yield technology, which is applied in the field of integrated circuit yield estimation method and memory based on interpolation adaptive importance sampling technology, can solve the problem of low efficiency of integrated circuit yield estimation algorithm, and achieve saving time and resources, The effect of reducing the number of sampling times and ensuring accuracy
Pending Publication Date: 2022-03-15
深圳国微福芯技术有限公司
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[0004] The purpose of the present invention is to provide an integrated circuit yield estimation method based on interpolation adaptive importance sampling technology for the defect that the efficiency of the integrated circuit yield estimation algorithm in the above-mentioned prior art is not high
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[0042]The invention provides an integrated circuit yield estimation method based on interpolation self-adaptive importance sampling technology, in which the construction of proposed distribution of importance sampling is the key, and the quality of proposed distribution structure directly affects the accuracy of yield estimation. The core idea of importance sampling is to construct a proposal distribution and move the sampling center to the failure area. The present invention performs yield estimation by introducing importance weights, so as to achieve the purpose of obtaining accurate yield estimation results with fewer sampling times. However, only constructing a proposed distribution for importance sampling will lose accuracy in the case of multiple failure domains. Therefore, the present invention clusters the failure sample points through the K center point clustering algorithm, and regards each cluster as a failure domain, respectively Importance sampling is performed i...
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The invention provides an integrated circuit yield estimation method and a memory, and the method comprises the steps: constructing initial proposal distribution, and carrying out the following iteration processes: carrying out importance sampling under the constructed proposal distribution, carrying out circuit simulation on generated sample points, and obtaining the performance parameters of each sample point; a plurality of failure points are determined according to the delimited performance boundary, the importance weight of each failure point is calculated, and then yield estimation is carried out; and calculating a quality factor of importance sampling according to the estimated yield and judging whether the quality factor of importance sampling reaches a set index, if so, exiting iteration and outputting the estimated yield, otherwise, updating the position parameter of the failure point through a linear interpolation method, constructing new proposal distribution, and carrying out iteration again. By adopting the technical scheme of the invention, the estimation efficiency of the yield of the integrated circuit can be improved.
Description
technical field [0001] The invention relates to the field of integrated circuits, in particular to an integrated circuit yield estimation method and memory based on interpolation self-adaptive importance sampling technology. Background technique [0002] When the integrated circuit manufacturing process reaches the deep nanometer node, due to process fluctuations in the manufacturing process, some related circuit parameters such as effective channel length, transistor threshold voltage, etc. may deviate from the rated value at the time of design, and these random errors cannot change The degree is reduced proportionally, and the impact of process fluctuation on the entire circuit is becoming more and more serious, resulting in a decline in product yield. At the same time, as the scale of the circuit increases, to ensure a high yield rate of the entire circuit, it is necessary to have an extremely low failure rate at the transistor level. This type of problem is called a very...
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IPC IPC(8): G06F30/3308G06F30/27G06K9/62G06F111/08
CPCG06F30/3308G06F30/27G06F2111/08G06F18/23
Inventor 赵文鹏苏东李鹏浩王华卓范文妍鲍琛白耿何元
Owner 深圳国微福芯技术有限公司