Astronavigation general gate-level logic modeling method for form verification

Abstract

The invention relates to an aerospace general gate-level logic modeling method for form verification, which is used for carrying out anti-radiation redundancy characteristic analysis and modeling on an anti-radiation hardening logic gate circuit of an aerospace-level large-scale integrated circuit, and carrying out form verification-based security attribute evaluation and logic completeness check on the aerospace-level large-scale integrated circuit based on the model. The problem of security attribute evaluation of the space navigation large-scale integrated circuit under the space radiation environment and the spacecraft high-reliability application condition is solved, the operation is simple and convenient, the automation degree is high, the evaluation efficiency is high, the evaluation operation links are reduced, and the evaluation operability is improved.

Description

technical field [0001] The invention relates to an aerospace general gate-level logic modeling method for formal verification, belonging to the field of spacecraft control software evaluation. Background technique [0002] The logic unit is the basic unit that constitutes an aerospace-grade VLSI. Through the safety performance evaluation based on the logic model of aerospace-level large-scale integrated circuits, the discovery, evaluation and improvement of incomplete logic design, logic loopholes and even design backdoors can be completed, avoiding the cycle and tape-out of resolving problems after tape-out Fee cost. In order to ensure the safe and reliable on-orbit application of aerospace large-scale integrated circuits, it is necessary to model the logic model, and measure and evaluate the device safety attributes based on this model. [0003] Spacecraft uses large-scale integrated circuits as a part of the core key components of spacecraft, and its security threatens ...

AI Technical Summary

Problems solved by technology

[0004] The technical problem solved by the present invention is: Aiming at the problem that in the current prior art, the logic model used for traditional formal verification cannot meet the evaluation and use requirements of aerospace-grade integrated circuits, a general-purpose gate-level logic modeling for aerospace for formal verification is proposed method

Images