Verification method and system for memory disambiguation in processor

Abstract

The invention relates to the technical field of processors, in particular to a verification method and system for memory disambiguation in a processor, memory disambiguation logic caused by single-core, multi-core and non-aligned access is verified by monitoring execution information of a load instruction and a store instruction in a DUT, and the memory disambiguation logic is verified by comparing a memory disambiguation result of the DUT with a memory disambiguation result of a checker. Judging whether the assembly line needs to be re-brushed or not and from which instruction the assembly line starts to be re-brushed; according to the method, the logic of memory disambiguation is verified, and single-core and multi-core memory disambiguation is supported at the same time. The final result of memory disambiguation is whether the assembly line needs to be re-refreshed and the instruction from which the assembly line needs to be re-refreshed, the verification method can accurately verify the two points, if the re-refreshed assembly line information is inconsistent with the DUT, error information can be immediately reported, and verification personnel can be helped to quickly and effectively debug codes.

Description

technical field [0001] The invention relates to the technical field of processors, in particular to a verification method and system for memory disambiguation in a processor. Background technique [0002] For processors with high-performance out-of-order execution, memory access instructions are often executed out of order, load instructions can adopt a speculative execution strategy, and store instructions must be guaranteed to be written into memory sequentially. After the load instruction obtains the physical address, it can try to obtain the data. During the trial process, the load instruction will search for a store instruction that has an address correlation with itself. If there is a younger store instruction with the same address, the load can be directly obtained from the The store instruction gets data. However, there are also some older store instructions whose physical addresses have not been obtained. Load can ignore these store instructions and obtain data. I...

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Problems solved by technology

[0003] Another situation that requires memory disambiguation occurs in a multi-core system. If two load instructions of core 0 access the same address, but for some reason the young load instruction executes first and obtains the data, then core 1 executes the The write operation changes the data, and then the old load instruction of the core 0 is executed. It obtains new data, while the young load instruction obtains old data. At this time, it is necessary to re-refresh the pipeline and re-execute the young load instruction

[0004] In conventional processor verification, separate modeling is performed for the memory access module, and the obtained access data is compared, but it is difficult to accurately verify the micro-architecture of memory disambiguation, especially in multi-core systems. Memory disambiguation verification requires full familiarity with the system and micro-architecture, and it is difficult to find related technologies on the market

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