SPI bus verification method and system based on UVM

Abstract

The invention discloses an SPI bus verification method and system based on a UVM. Ports of two spi modules are correspondingly connected to serve as DUTs, and the ports are SPI0 and SPI1. According to the technical scheme, the method comprises the following steps of: firstly, respectively setting a UVM (Universal Verification Model)-based ahb verification platform based on a UVM (Universal Verification Model) and a UVM (Universal Verification Model), respectively connecting the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM-based ahb verification platform with the UVM And access can be realized through an ahb bus with higher performance. Different modes of the spi module can be verified at the same time in the same testcase, and the verification time is greatly shortened.

Description

technical field [0001] The invention belongs to the technical fields of SPI bus verification and chip verification, and in particular relates to a UVM-based SPI bus verification method and system. Background technique [0002] As the complexity and scale of chips continue to increase, it is more likely to cause errors in the complex design process of the chip, which brings great challenges to the verification work of the chip. The higher the value, the more attention chip designers pay to the verification work of the chip. In the entire chip design cycle, the verification work has exceeded the design time by 60%-70%, which has become a general consensus in the industry. Due to the urgent need of verification work, a variety of chip verification methods have emerged. In 2006, Synopsys launched the VMM verification methodology, which integrated the register solution RAL (Register Abstraction Layer); in 2008, Cadence and Mentor introduced the OVM verification methodology, whic...

AI Technical Summary

Problems solved by technology

Therefore, it is impossible to quickly build a verification platform

[0008] 2. There is no verification of the interconnection between spi and higher performance buses (such as ahb)

[0009] 3. It is impossible to realize the verification of running in SPI master and slave modes at the same time

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