FPGA program dynamic loading device and method and satellite signal acquisition preprocessing board card
A technology of satellite signal acquisition and dynamic loading, which is applied in the direction of program control device, program loading/starting, etc., can solve the complex, time-consuming and labor-intensive process of rewriting FPGA, and achieve the effect of improving the convenience of rewriting
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0037] figure 1 A schematic structural diagram of an FPGA program dynamic loading device according to an embodiment of the present invention is shown.
[0038] Such as figure 1 As shown, an FPGA program dynamic loading device is applied to a satellite signal acquisition preprocessing board, including: a first FPGA chip 1, a second FPGA chip 2 and a storage module 3;
[0039] The second FPGA chip 2 is respectively connected with the first FPGA chip 1, the storage module 3 and the upper computer 4;
[0040] The host computer 4 is used to compile and store the algorithm program that the first FPGA chip 1 operates;
[0041] The first FPGA chip 1 is used to run an algorithm program to process satellite signal data;
[0042] The storage module 3 is used to store the operating program of the second FPGA chip 2;
[0043] The second FPGA chip 2 is used for:
[0044] Read the operating program from the storage module 3 and start it, and obtain the algorithm program from the upper c...
Embodiment 2
[0057] A kind of FPGA program dynamic loading method, be applied to the FPGA program dynamic loading device of embodiment 1, method comprises:
[0058] Step S101: After the satellite signal acquisition preprocessing board is powered on, the second FPGA chip 2 reads the operating program from the storage module 3 and starts it;
[0059] Step S102: the second FPGA chip 2 obtains the algorithm program from the host computer 4 and loads the algorithm program into the first FPGA chip 1;
[0060] Step S103: the first FPGA chip 1 runs an algorithm program to process satellite signal data;
[0061] Step S104: After the host computer 4 rewrites the algorithm program, the second FPGA chip 2 loads the algorithm program rewritten by the host computer 4 into the first FPGA chip 1;
[0062] Step S105: The first FPGA chip 1 runs the rewritten algorithm program to process the satellite signal data.
[0063] Specifically, in this embodiment, two FPGAs are set on the circuit board, the second...
Embodiment 3
[0065] A satellite signal acquisition preprocessing board includes the FPGA program dynamic loading device of Embodiment 1.
[0066] The satellite signal acquisition preprocessing board of the present embodiment also includes other modules of the existing board, such as the satellite chip connected with the first FPGA chip 1, etc., the first FPGA chip 1 receives the satellite data of the satellite chip, and according to the digital clock The signal preprocesses the satellite data.
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More