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Memory device including phase change memory cell and method of operating same

A phase-change storage and storage device technology, applied in the field of semiconductor memory, can solve the problems of poor high-speed cell distribution, phase-change storage deterioration, etc.

Pending Publication Date: 2022-04-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Large write currents lead to degradation of phase change storage, or make the distribution of high-speed cells worse

Method used

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  • Memory device including phase change memory cell and method of operating same
  • Memory device including phase change memory cell and method of operating same
  • Memory device including phase change memory cell and method of operating same

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Experimental program
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Embodiment Construction

[0029] Hereinafter, the embodiments of the present disclosure can be described in detail and clearly to the extent that those skilled in the art can easily implement the present disclosure.

[0030] figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure. refer to figure 1 , the memory device 100 may include a memory cell array 110, a row decoder (X-DEC) (hereinafter referred to as "X decoder") 120, a column decoder (Y-DEC) (hereinafter referred to as "Y decoder") device") 130, voltage bias circuit 140, current bias circuit 150 and control logic circuit 160.

[0031] The memory cell array 110 may include a plurality of memory cells. A plurality of memory cells may be connected to word lines WL and bit lines BL.

[0032] The X decoder 120 may be connected to the memory cell array 110 through a plurality of word lines WL. The X decoder 120 may be configured to control voltage levels of a plurality of word lines WL. For ...

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PUM

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Abstract

A memory device including a phase change memory cell and a method of operating the same are provided. The memory device includes a phase change memory (PCM) cell connected between a bit line and a word line. During a reset operation, the X decoder provides a word line voltage to the word line, and during the reset operation, the Y decoder provides a bit line voltage to the bit line. The voltage bias circuit generates a word line voltage and a bit line voltage based on a first bias during a first period of a reset operation, and generates the word line voltage and the bit line voltage based on a second bias greater than the first bias during a second period of the reset operation, the word line voltage and the bit line voltage are generated based on a third bias less than the first bias and the second bias during a third period of the reset operation.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application No. 10-2020-0133765 filed in the Korean Intellectual Property Office on October 15, 2020, the entire disclosure of which is incorporated herein by reference. technical field [0003] Embodiments of the present disclosure described herein relate to semiconductor memories, and more particularly, to memory devices including phase change memory cells and methods of operating the same. Background technique [0004] Semiconductor memories are classified as: volatile memories in which stored data disappears when the power is turned off, such as static random access memory (SRAM) or dynamic random access memory (DRAM); Nonvolatile memory that remains constant even when interrupted, such as flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM). [0005] For example, phase change memory (PCM) stores data by u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C13/00
CPCG11C13/0002G11C13/0026G11C13/0028G11C13/0038G11C13/0004G11C13/0069G11C13/0097G11C2013/0092G11C13/003G11C2213/76G11C2013/0078G11C2213/15G11C13/0061G11C13/0007G11C8/10
Inventor 李埈圭朴贤国金钟律
Owner SAMSUNG ELECTRONICS CO LTD