Readout circuit structure

A technology for reading out circuits and bits, applied in information storage, static memory, digital memory information and other directions, which can solve the problems of long data readout time and long readout process time of sense amplifiers.

Pending Publication Date: 2022-04-22
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004]However, in the current DRAM data readout process, the time between row opening and column opening is the charge sharing stage of the sense amplifier, and the...

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Embodiment Construction

[0063] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Preferred embodiments of the application are shown in the accompanying drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

[0065] In the drawings, the dimensions of layers and r...

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Abstract

The invention relates to a readout circuit structure. The readout circuit structure comprises a first N-type active region and a first grid electrode arranged on the first N-type active region; a second N-type active region and a second grid electrode arranged on the second N-type active region; a first P-type active region and a third grid electrode arranged on the first P-type active region; a second P-type active region and a fourth grid electrode arranged on the second P-type active region; the first isolation grid electrode is arranged on the first active region, and the first isolation grid electrode is used for forming a first isolation tube; the second isolation grid is arranged on the second active region and is used for forming a second isolation tube, one end of the first isolation tube is connected with the first read-out bit line, the other end of the first isolation tube is connected with the initial bit line, one end of the second isolation tube is connected with the first complementary read-out bit line, and the other end of the second isolation tube is connected with the initial complementary bit line; according to the invention, the data reading duration can be effectively reduced.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a readout circuit structure. Background technique [0002] Memory timings are four parameters describing the performance of Dynamic Random Access Memory (DRAM), including: CAS latency (CL), row address to column address delay (tRCD), row precharge time ( tRP) and row activity time (tRAS). [0003] The row address to column address delay tRCD refers to the minimum number of clock cycles required to open a row of memory and access its columns. In the design process of DRAM, the time interval t from row opening to column opening needs to be greater than tRCD, so as to ensure that The data in the memory cell is correctly read. [0004] However, in the current data readout process of DRAM, the time between the row opening and the column opening is the charge sharing stage of the sense amplifier. The delay of tRCD is ensured by the time of the charge sharing sta...

Claims

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Application Information

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IPC IPC(8): G11C7/10G11C7/12
CPCG11C7/1051G11C7/12
Inventor 杨桂芬
Owner CHANGXIN MEMORY TECH INC
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