Readout circuit structure

Abstract

The invention relates to a readout circuit structure. The readout circuit structure comprises a first N-type active region and a first grid electrode arranged on the first N-type active region; a second N-type active region and a second grid electrode arranged on the second N-type active region; a first P-type active region and a third grid electrode arranged on the first P-type active region; a second P-type active region and a fourth grid electrode arranged on the second P-type active region; the first isolation grid electrode is arranged on the first active region, and the first isolation grid electrode is used for forming a first isolation tube; the second isolation grid is arranged on the second active region and is used for forming a second isolation tube, one end of the first isolation tube is connected with the first read-out bit line, the other end of the first isolation tube is connected with the initial bit line, one end of the second isolation tube is connected with the first complementary read-out bit line, and the other end of the second isolation tube is connected with the initial complementary bit line; according to the invention, the data reading duration can be effectively reduced.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a readout circuit structure. Background technique [0002] Memory timings are four parameters describing the performance of Dynamic Random Access Memory (DRAM), including: CAS latency (CL), row address to column address delay (tRCD), row precharge time ( tRP) and row activity time (tRAS). [0003] The row address to column address delay tRCD refers to the minimum number of clock cycles required to open a row of memory and access its columns. In the design process of DRAM, the time interval t from row opening to column opening needs to be greater than tRCD, so as to ensure that The data in the memory cell is correctly read. [0004] However, in the current data readout process of DRAM, the time between the row opening and the column opening is the charge sharing stage of the sense amplifier. The delay of tRCD is ensured by the time of the charge sharing sta...

AI Technical Summary

Problems solved by technology

[0004]However, in the current DRAM data readout process, the time between row opening and column opening is the charge sharing stage of the sense amplifier, and the time passing through the charge sharing stage Guaranteed delay in tRCD, resulting in longer sense amplifier read flow time, resulting in longer data read time from DRAM

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