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Three-dimensional vertical memory readout circuit and readout method thereof

A readout circuit, vertical type technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problem of long readout time of the readout circuit, achieve a wide range of applications, reduce misreading, reduce The effect of reading time

Active Publication Date: 2020-03-24
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a three-dimensional vertical memory readout circuit and a readout method thereof, which are used to solve the problems of long readout time and errors in the existing three-dimensional vertical memory readout circuit. read problem

Method used

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  • Three-dimensional vertical memory readout circuit and readout method thereof
  • Three-dimensional vertical memory readout circuit and readout method thereof
  • Three-dimensional vertical memory readout circuit and readout method thereof

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Embodiment 1

[0097] Such as image 3 and Figure 4 As shown, this embodiment provides a three-dimensional vertical memory readout circuit, and the three-dimensional vertical memory readout circuit 1 includes:

[0098] A three-dimensional vertical memory 10, said three-dimensional vertical memory 10 comprising at least one three-dimensional vertical memory sub-array 13 connected to at least one word line 11 in the horizontal direction and connected to at least one bit line 12 in the vertical direction, said The three-dimensional vertical memory sub-array 13 includes at least one array page 131 and a source line 132 connected to the array page 131, wherein the array page 131 includes the word line 11 in the horizontal direction, and passes through the first line in the vertical direction. The vertical transistor 1311 is connected to at least one local bit line 1312 corresponding to the bit line 12, and the memory cell 1313 located at the intersection of the word line 11 and the local bit li...

Embodiment 2

[0139] Such as Figure 3 to Figure 7 As shown, this embodiment provides a readout method of the three-dimensional vertical memory readout circuit as described in Embodiment 1, and the readout method includes:

[0140] Selecting a source line, a word line and a bit line, connecting the selected memory cells in the three-dimensional vertical memory sub-array to a sense amplifier, and the sense amplifier reads the read current of the selected memory cells; at the same time , the read reference circuit starts to work to generate a dynamic read reference current;

[0141] The sense amplifier compares the read current of the selected memory cell with the read reference current, and reads out the data stored in the selected memory cell according to the comparison result;

[0142] Wherein, the parasitic parameters of the bit line and the leakage on the bit line, the leakage on the word line, the parasitic parameters of the vertical transistor, and the parasitic parameters of the read...

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Abstract

The invention provides a three-dimensional vertical memory reading circuit and a reading method thereof. By introducing bit line parasitic parameters, electric leakage on bit lines, electric leakage on word lines, vertical transistor parasitic parameters and reading transmission gate parasitic parameters to offset the bit line parasitic effect of semi-gate storage units, electric leakage on the bit lines, electric leakage on the word lines, the first vertical transistor parasitic effect and the first reading transmission gate parasitic effect respectively, the transient value of a reading reference current is within the range from a reading low-resistance current to a reading high-resistance current, therefore, the pseudo reading phenomenon is eliminated, the signal reading time is shortened, and the misreading condition is reduced. According to the three-dimensional vertical memory reading circuit and the reading method thereof, the problems that an existing three-dimensional verticalmemory reading circuit is long in reading time and has the misreading condition are solved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a three-dimensional vertical memory readout circuit and a readout method thereof. Background technique [0002] Three-dimensional integrated circuit (3D-IC) is a key technology for the integrated circuit industry to surpass Moore's Law. Three-dimensional integrated circuits can be divided into wafer-wafer stacking, die-wafer stacking and monolithic three-dimensional integrated circuits. Among them, the three-dimensional memory belonging to the monolithic three-dimensional integrated circuit has the fastest development. [0003] Integrated circuit memory is widely used in industrial and consumer electronics. According to whether the memory can be stored without power, it can be divided into volatile memory and non-volatile memory. Non-volatile memory includes flash memory (flash memory), magnetic memory (magnetoresistive random-access memory, MRAM), resistive random...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C8/14G11C8/08G11C7/18G11C7/12G11C7/10
Inventor 雷宇陈后鹏宋志棠
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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