Capacitance calibration method for successive approximation type ADC (Analog to Digital Converter)

Abstract

The invention discloses a capacitance calibration method for a successive approximation type ADC (Analog to Digital Converter). The capacitance calibration method comprises the following steps: initializing differential mode digital weights and single-ended mode digital weights of all capacitors to be calibrated in a switched capacitor module according to digital weights of ideal capacitors; obtaining the actual digital weight of each capacitor to be calibrated in the differential mode in sequence, and assigning the digital weight corresponding to the differential mode; sequentially acquiring the actual digital weight of each capacitor to be calibrated in the single-ended mode, and assigning the actual digital weight to the corresponding single-ended mode digital weight; assigning each differential mode digital weight or each single-ended mode digital weight to each actual final digital weight according to the selected differential mode or single-ended mode; and adding the analog output signal of the successive approximation type ADC by bit by using each actual final digital weight to obtain a digital output signal. According to the invention, self-calibration of the capacitor can be realized, and an additional calibration capacitor array is not needed.

Description

technical field [0001] The invention relates to the field of analog-to-digital converters, in particular to a capacitance calibration method for a successive approximation (SAR) type ADC (analog-to-digital converter). Background technique [0002] figure 2 It is a schematic diagram of an existing successive approximation analog-to-digital converter (SAR ADC), which generally includes switched capacitors, comparators, and SAR logic. The switched capacitor block is used for sampling and converting the digital output of the comparator into an analog signal with analog weights. The comparator is used to judge the analog signal of the switched capacitor module into a digital signal. The SAR logic module is used to control the logic control of the successive approximation, and feeds back the result of the comparator to the switched capacitor module bit by bit, and outputs the quantization result of the ADC at the same time. When the resolution of the ADC is high, a calibration ...

AI Technical Summary

Problems solved by technology

[0003] In a SAR ADC, one of the important accuracy limitations is the capacitance mismatch

To solve the limitation of matching accuracy, one of the traditional solutions is to increase the size of the capacitor to physically obtain higher matching accuracy, but this will increase the layout area and reduce the speed of the ADC. The increased area of ​​this solution will increase with the resolution. The increase of exponential growth, when the resolution is greater than 12bit, the required area is huge

Another method is capacitance calibration. Traditional capacitance calibration requires an additional calibration capacitor array, which increases the layout area.

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