Dynamic successive approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration system and method

Abstract

A time-interleaved SAR-ADC employs a calibrated SAR-ADC circuit to convert the sampled voltage level into serial digital data. A variable delay clock circuit synchronizes clock signals received at respective SAR-ADCs with sampling points of analog serial data. The IC and environmental fluctuations result in a delay in the variable delay clock circuit, thereby skewing the clock signal. The calibrated SAR-ADC detects a delay change in the variable delay clock circuit. By delaying a first clock signal in a variable delay clock circuit, and comparing a phase of the delayed clock signal to a phase shifted clock signal having a known phase shift relative to the first clock signal, a change in delay of the variable delay clock circuit may be detected as a phase difference. Based on the indication of the phase difference, a delay control signal is generated to control the delay in the variable delay clock.

Description

technical field [0001] The techniques of the present disclosure relate to analog-to-digital converter (ADC) circuits, and more particularly, to receiving analog data on a high-speed serial interface and converting the serial data to digital using a successive approximation register (SAR) ADC (SAR-ADC) / binary value. Background technique [0002] The speed at which processors in integrated circuits (ICs) process binary data continues to increase. Binary data to be processed must be provided to the processor at a rate high enough to avoid the processor waiting for data. A video processor is an example of a type of processor to which large amounts of binary data are transferred at high rates, but other types of processors have similar capabilities. The data communication interface periodically sends and receives binary data in the IC at a high frequency. Data can be sent or received every cycle of a reference clock that can be derived from the periodically varying data. Lar...

AI Technical Summary

Problems solved by technology

The voltage level of a time-varying analog signal sampled outside of the sampling point in the data clock cycle may not accurately represent the transmitted data

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