Hardware dynamic configuration method based on deep learning accelerator
A technology of deep learning and configuration method, applied in the direction of processor architecture/configuration, software reuse, creation/generation of source code, etc., can solve problems such as complex process, difficult development, and inability to quickly re-design, so as to reduce complexity sexual effect
Pending Publication Date: 2022-05-06
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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Problems solved by technology
However, the process of traditional FPGA logic design is complex and difficult to develop, and it cannot be redesigned quickly; in addition, deep learning algorithms based on neural networks usually require repeated iterations (retraining) in the process of use. The acceleration system usually only supports customized algorithms, and the algorithm adaptability and quick configuration flexibility are poor
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[0029] Embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.
[0030] Embodiments of the present application are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. The present application can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all...
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The invention provides a hardware dynamic configuration method based on a deep learning accelerator, and belongs to the technical field of embedded computing, and the configuration method comprises the steps: receiving a deep learning algorithm needing to be accelerated; and extracting a weight parameter and a threshold parameter of the target algorithm, and sending the weight parameter and the threshold parameter to the accelerator by the main processor through a parameter packet so as to complete dynamic loading of the parameters, thereby completing rapid reconstruction of the accelerator. Through the processing scheme provided by the invention, the heterogeneous computing system for accelerating the deep learning algorithm becomes more flexible.
Description
technical field [0001] This application relates to the field of embedded computing, and in particular to a method for dynamically configuring hardware based on deep learning accelerators. Background technique [0002] With the development of deep learning, the application of deep learning technology in various industrial fields has become the mainstream trend in the future. With the rapid development of deep learning technology, great progress has been made in the fields of image processing, speech processing, human-computer interaction, intelligent decision-making, automatic control, etc., followed by the continuous increase in the complexity of deep learning methods, which has a great impact on computing resources. The ever-increasing demand for computing systems also puts forward new requirements for the hardware and software architecture of computing systems. Using FPGA as an accelerator in a heterogeneous system has been proven to be one of the effective ways to solve ...
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Login to View More IPC IPC(8): G06N3/063G06N3/04G06T1/20G06F8/36
CPCG06N3/063G06T1/20G06F8/36G06N3/045G06N3/044
Inventor 石添介刘飞阳田径赵一煊李亚晖文鹏程
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA