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Display panel

A display panel and display area technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of insufficient IC thrust, increased risk of crosstalk, and large signal load, so as to avoid insufficient thrust, reduce signal load, and improve stability sexual effect

Pending Publication Date: 2022-05-13
WUHAN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the setting of fanout routing also brings some problems in the display area. For example, the parasitic capacitance between the fanout routing and the signal line in the pixel leads to a large signal loading, which leads to insufficient IC thrust and increased risk of crosstalk.

Method used

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041] combine figure 1 and figure 2 As shown, the embodiment of the present application provides a display panel 1, the display panel 1 has a display area 2 and a binding area 3 located on one side of the display area 2; the display panel 1 includes an array located at the display area 2 and the binding area 3 The substrate 4 , a plurality of fan-out lines 5 on the array substrate 4 , and an organic light-emitting layer 6 located on a side of the plurality of fan-out lines 5 away from the array substrate 4 and electrically connected to the array substrate 4 .

[0042] The array substrate 4 includes a plurality of signal lines 7 located in the display area 2 and arranged at intervals in a first direction (such as a horizontal direction); each signal line 7 is arranged along a second direction (such as a vertical direction) perpendicular to the first direction. extend.

[0043] Specifically, such as figure 2 As shown, the array substrate 4 also includes a substrate 8, a bu...

Embodiment 2

[0067] Such as figure 1 , Figure 4 and Figure 5 As shown, the embodiment of the present application also provides a display panel 1, which is different from the first embodiment above in that the display panel 1 in the embodiment of the present application also includes And the shielding layer 42 provided corresponding to the multiple fan-out wirings 5 ​​; the shielding layer 42 is electrically connected to the power supply voltage signal line 19 .

[0068] Specifically, such as Figure 5 As shown, the shielding layer 42 includes a plurality of shielding traces 43 corresponding to the plurality of fanout traces 5; the width of the shielding traces 43 is greater than or equal to the width of the corresponding fanout traces 5, and less than or equal to the corresponding The width of the signal line 7. It can be understood that each shielding wire 43 is connected to the VDD signal.

[0069] Specifically, such as Figure 4 As shown, the masking layer 42 is located on the s...

Embodiment 3

[0073] Such as figure 1 and Figure 6 As shown, the embodiment of the present application also provides a display panel 1, which is different from the first embodiment above in that the power supply voltage signal line 19 in the embodiment of the present application includes the first layer stacked in different layers in the direction perpendicular to the array substrate 4. A sub power supply voltage signal line 46 and a second sub power supply voltage signal line 47; wherein, the first sub power supply voltage signal line 46 is electrically connected to the second sub power supply voltage signal line 47; the data line 18 is connected to the second sub power supply voltage signal line 47 same floor settings. It can be understood that an insulating layer is provided between the first sub-supply voltage signal line 46 and the second sub-supply voltage signal line 47 , that is, the first planar layer 33 hereinafter.

[0074] Specifically, such as Figure 6 As shown, the displa...

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PUM

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Abstract

The invention discloses a display panel which is provided with a display area and a binding area. The display panel comprises an array substrate located in a display area and a binding area and a plurality of fan-out wires located on the array substrate. The array substrate comprises a plurality of signal lines which are located in the display area and arranged at intervals in the first direction. The signal lines extend along a second direction perpendicular to the first direction; the fan-out wires are located in the display area and electrically connected with at least part of the signal wires in a one-to-one correspondence mode. The fan-out wire comprises a first wire part which is arranged close to the binding area and extends along the second direction and a second wire part which is connected with one end, far away from the binding area, of the first wire part and extends along the first direction; each first wiring part is overlapped with one of the signal lines in the direction perpendicular to the array substrate, and the end, away from the first wiring part, of each second wiring part is electrically connected with the corresponding signal line. According to the invention, stray capacitance generated between the fan-out wire and each signal of the display area can be reduced.

Description

technical field [0001] The present application relates to the field of display technology, in particular to a display panel. Background technique [0002] As the proportion of OLED (Organic Light Emitting Display, Organic Light Emitting Display) panel display area continues to increase, the design space left for the frame (Border) is continuously compressed, and the irregular design of the panel frame makes the original conventional design unable to meet the requirements. . [0003] In the Border design, the part that takes up a relatively large proportion of the space is the part where the signal lines drawn from the IC (integrated circuit) enter the display area. Generally, the leads are distributed in a fan shape, also known as fanout (fan-out) routing. In conventional designs, the fanout routing is generally located in the non-display area. In recent years, in order to compress the space of the fanout wiring, the line width and line spacing of the fanout wiring can be ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/32
CPCH10K59/131
Inventor 何正霞吴绍静李彦阳周坤
Owner WUHAN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD