Display panel
A display panel and display area technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of insufficient IC thrust, increased risk of crosstalk, and large signal load, so as to avoid insufficient thrust, reduce signal load, and improve stability sexual effect
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Embodiment 1
[0041] combine figure 1 and figure 2 As shown, the embodiment of the present application provides a display panel 1, the display panel 1 has a display area 2 and a binding area 3 located on one side of the display area 2; the display panel 1 includes an array located at the display area 2 and the binding area 3 The substrate 4 , a plurality of fan-out lines 5 on the array substrate 4 , and an organic light-emitting layer 6 located on a side of the plurality of fan-out lines 5 away from the array substrate 4 and electrically connected to the array substrate 4 .
[0042] The array substrate 4 includes a plurality of signal lines 7 located in the display area 2 and arranged at intervals in a first direction (such as a horizontal direction); each signal line 7 is arranged along a second direction (such as a vertical direction) perpendicular to the first direction. extend.
[0043] Specifically, such as figure 2 As shown, the array substrate 4 also includes a substrate 8, a bu...
Embodiment 2
[0067] Such as figure 1 , Figure 4 and Figure 5 As shown, the embodiment of the present application also provides a display panel 1, which is different from the first embodiment above in that the display panel 1 in the embodiment of the present application also includes And the shielding layer 42 provided corresponding to the multiple fan-out wirings 5 ; the shielding layer 42 is electrically connected to the power supply voltage signal line 19 .
[0068] Specifically, such as Figure 5 As shown, the shielding layer 42 includes a plurality of shielding traces 43 corresponding to the plurality of fanout traces 5; the width of the shielding traces 43 is greater than or equal to the width of the corresponding fanout traces 5, and less than or equal to the corresponding The width of the signal line 7. It can be understood that each shielding wire 43 is connected to the VDD signal.
[0069] Specifically, such as Figure 4 As shown, the masking layer 42 is located on the s...
Embodiment 3
[0073] Such as figure 1 and Figure 6 As shown, the embodiment of the present application also provides a display panel 1, which is different from the first embodiment above in that the power supply voltage signal line 19 in the embodiment of the present application includes the first layer stacked in different layers in the direction perpendicular to the array substrate 4. A sub power supply voltage signal line 46 and a second sub power supply voltage signal line 47; wherein, the first sub power supply voltage signal line 46 is electrically connected to the second sub power supply voltage signal line 47; the data line 18 is connected to the second sub power supply voltage signal line 47 same floor settings. It can be understood that an insulating layer is provided between the first sub-supply voltage signal line 46 and the second sub-supply voltage signal line 47 , that is, the first planar layer 33 hereinafter.
[0074] Specifically, such as Figure 6 As shown, the displa...
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