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Overlay error compensation method and photoetching exposure method

A compensation method and overlay error technology, applied in microlithography exposure equipment, photolithography exposure equipment, optics, etc., can solve problems such as quasi-deviation

Pending Publication Date: 2022-05-20
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

For this reason, this application proposes an overlay error compensation method and a photolithographic exposure method to solve the problem of misalignment

Method used

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  • Overlay error compensation method and photoetching exposure method
  • Overlay error compensation method and photoetching exposure method
  • Overlay error compensation method and photoetching exposure method

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Embodiment Construction

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0018] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for the purpose of clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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Abstract

The invention relates to the field of semiconductor manufacturing, in particular to an overlay error compensation method and a photoetching exposure method.The overlay error compensation method comprises the following steps that a wafer is provided, and the wafer is provided with an alignment mark; loading the wafer, and measuring a first position of the alignment mark; overturning the wafer by 180 degrees, measuring a second position of the alignment mark, and calculating a position error between the first position and the second position; and calculating the compensation amount of the alignment mark, and then performing compensation. Compared with the prior art, the embodiment of the invention has the advantages that a TIS (Tool-Induced Shift) compensation method is applied to error compensation of the alignment mark, so that the problem of alignment deviation of the alignment mark is solved.

Description

technical field [0001] The present application relates to the field of semiconductor manufacturing, in particular to an overlay error compensation method and a photolithography exposure method. Background technique [0002] Photolithography is an important step in the manufacturing process in the semiconductor field. Photolithography is the process of transferring the mask pattern on the mask plate (Mask) to the wafer (Wafer) through a series of steps such as alignment and exposure. In the manufacturing process of semiconductor chips, a multi-layer photolithography process to complete the entire manufacturing process. [0003] With the development of semiconductor manufacturing technology and the development of integrated circuit design and manufacturing, photolithographic imaging technology has developed accordingly, and the feature size of semiconductor devices has also been continuously reduced. In order to achieve good product performance and high yield, how to control...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/20
CPCG03F7/70633G03F7/70616
Inventor 田范焕梁时元贺晓彬李亭亭杨涛刘金彪
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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