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Memory array

A technology of memory array and storage tube, applied in the field of memory array, can solve the problems of complicated peripheral circuit design and occupation of storage devices, etc., and achieve the effect of saving area and simple design.

Pending Publication Date: 2022-05-31
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The present application provides a memory array, which can solve at least one of the problems that in the existing memory arrays, source lines need to be arranged in the lateral direction, resulting in memory devices occupying a large chip design area and peripheral circuit design being too complicated

Method used

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Embodiment Construction

[0033] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0034] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...

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Abstract

The invention provides a memory array which comprises a plurality of memory units, a plurality of bit lines, a plurality of selection tube word lines and a plurality of selection tube word lines, the memory units form an array with m rows and n columns, and each memory unit comprises a selection tube and a memory tube which are connected in series; and the source electrodes and the grid electrodes of the selection tubes are connected, and the grid electrodes of the selection tubes in the same row are connected with the corresponding selection tube word lines. According to the invention, the selection tube and the storage tube are adjacently arranged in a back-to-back manner, so that compared with a traditional SONOS device with a two-tube (selection tube and storage tube) separation structure, the SONOS device saves more area. Furthermore, the source electrode and the grid electrode of the selection tube in each storage unit are connected together, so that a source line is omitted, and the design of an external circuit is simpler.

Description

technical field [0001] The present application relates to the technical field of storage devices, in particular to a memory array. Background technique [0002] Please refer to figure 1 , figure 1 It is a structural diagram of a traditional common-source two-tube array arrangement. This storage device includes: a plurality of storage units arranged in an array, and each storage unit consists of a storage tube and a selection tubes in series. Such as figure 1 As shown, the memory cells A1, A2, B1, and B2 form a 2*2 array, and the bit lines of the memory cells in different columns are BL1 and BL2 respectively, and the word lines can be divided into a selection pipe word line (WL) and a memory pipe word line. Line (WLS), WLS horizontally connects the gates of the storage transistors in the same row together, WL horizontally connects the gates of the selection transistors in the same row together, the storage transistor word lines are respectively WLS1 and WLS2, and the sele...

Claims

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Application Information

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IPC IPC(8): G11C5/02G11C5/06G11C7/12G11C7/18G11C8/08G11C8/14
CPCG11C5/025G11C5/063G11C7/12G11C7/18G11C8/08G11C8/14G11C16/08G11C16/0433G11C16/10G11C16/16G11C16/24G11C16/26G11C16/0466
Inventor 王宁张可钢
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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