Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for identifying hot spots and transistors in photoetching active region

A technology of active regions and transistors, applied in the field of identifying irregular active regions and transistors in layouts, can solve problems such as unfavorable and no particularly effective methods for transistors, and achieve the effect of improving production technology

Pending Publication Date: 2022-07-01
SEMITRONIX
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prior art, there is no particularly effective method for identifying hot spots in lithographic active regions or transistors in these lithographic active regions, which is unfavorable for the further improvement of lithographic process and design

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for identifying hot spots and transistors in photoetching active region
  • Method for identifying hot spots and transistors in photoetching active region
  • Method for identifying hot spots and transistors in photoetching active region

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] like image 3 shown and incorporated by reference Figure 4 , Figure 5 , the method for identifying hot spots in an active area of ​​lithography in Embodiment 1 of the present invention includes: step S1. Obtaining layout information, including active area pattern, gate pattern and M0; the M0 is used to connect the active area. As each board layer has its own characteristics and the role it plays in the device, the graphics in each board layer will be different. In this embodiment, the M0 is preferably a metal layer, and in this embodiment, it is a metal layer M0, but in some embodiments, M0 is not a metal, which is not limited herein. Step S2. The silhouette edges that are connected in all or part of the active region graphics are perpendicular to each other, forming a first corner with an inner angle of 90° and a second corner with an inner angle of 270°, defining the vertex of the first corner and the second corner. The edge between the vertices of the corner is ...

Embodiment 2

[0034] Also for the convenience of description, in this embodiment, the extension direction of the gate electrode is the vertical direction, and the direction perpendicular to the extension direction of the gate electrode is the horizontal direction. In this embodiment, as Image 6 As shown, the main difference between the second embodiment and the first embodiment is that in the step S1, after acquiring the layout information, the vertical silhouette edge of the active region pattern in the overlapping area of ​​the active region pattern and the gate pattern is also , judging whether the vertical silhouette edge overlaps with the vertical silhouette edge of the gate pattern, and determining subsequent processing according to the judgment result.

[0035] In the layout of this embodiment, if the vertical silhouette edge overlaps with the vertical silhouette edge of the gate pattern, then step S2 is directly performed; however, when the vertical silhouette edge does not overlap...

Embodiment 3

[0038] The difference between the third embodiment of the present invention and the first embodiment mainly lies in that the non-active region formed by two adjacent L-shaped irregular active regions is identified in step S4 or after it is identified as U-shaped non-active regions. The regular active area, denoted as Ushape_space, is used to locate hot spots in the active area of ​​lithography. like Figure 7 shown.

[0039] The specific process of identifying the U-shaped irregular active region includes: connecting two first corner vertices in adjacent corner groups, connecting two second corner vertices, and an area enclosed by two opposite initial edges edge_ori Polygons that do not overlap with the active area shape in the Ushape_space are identified as Ushape_space. In this embodiment, the information of Ushape_space is also recorded, including: the lengths of the two side edges overlapping with edge_ori are denoted as Ushape_h1 and Ushape_h2; the length of the side ed...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for identifying hot spots in a photoetching active region. The method comprises the following steps: acquiring layout information; defining an initial edge; and identifying the residual rectangular region in the active region pattern except the region overlapped with the gate pattern as a first rectangle, and identifying the first rectangle in contact with the first short edge as an L-shaped irregular active region, namely photoetching active region hot spots. The invention also provides a method for identifying the transistor in the photoetching active region, the hot spots of the photoetching active region identified by the method provided by the invention can be used for identifying and acquiring the attribute information of the transistor in the photoetching active region, the process is simple, the result is visual, and the improvement of the production process and the improvement of the efficiency are facilitated.

Description

technical field [0001] The present invention relates to the field of semiconductor design and production, in particular to a method for identifying an irregular active area in a layout and a transistor therein. Background technique [0002] As integrated circuit production process technology nodes continue to advance, the design of integrated circuits becomes more and more complex. The mainstream lithography process used in the production of integrated circuits today has a wavelength of 193 nm. In the case where the wavelength of the exposure machine is not updated, the size of the exposure pattern is continuously reduced, and many lithography patterns that meet the design rules but have a poor actual process window are generated, which are called lithography defect hot spots, generally referring to the layout. A pattern or pattern combination that has a certain geometric feature and a feature size within a certain range that is likely to cause lithography defects. [0003...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/392G06F30/398G06F30/3323
CPCG06F30/392G06F30/398G06F30/3323
Inventor 潘伟伟杨璐丹蓝帆
Owner SEMITRONIX