Chip input and output module arrangement method and device and storage medium

Abstract

The invention discloses a chip input and output module arrangement method and device and a storage medium. The method comprises the following steps: firstly, determining one or more communication regions for arranging input and output modules at the peripheral boundary of a chip, and a soldering tin bump needing to pass through a GPIO (General Purpose Input / Output) outgoing line on the chip; and automatically placing an input / output module in the communication area, wherein module groups are placed in a one-to-one correspondence manner with the soldering tin bumps adjacent to the boundary. The embodiment of the invention further provides a device for implementing the method. According to the embodiment of the invention, automatic arrangement of the input and output modules of the chip can be adaptively realized, so that the input and output modules of the chip meet the requirements of wire outgoing rationality and signal integrity, and the arrangement efficiency is greatly improved.

Description

technical field [0001] The present disclosure relates to, but is not limited to, chip technology, and more particularly, to a method, device, and storage medium for arranging chip input and output modules. Background technique [0002] With the development of Moore's Law, the chip scale is further reduced, which puts forward higher requirements for chip design. The chip input and output module (IO: Input and Output) is an important part of the chip design. It is mainly used to input the external signals required for the chip to work and output the processed signals to the outside world. There are also some other modules for assist in this work. Common chip IOs include general purpose input / output modules (GPIO: General Purpose Input / Output), power supply modules, power control modules, termination modules, corner modules, common filling modules, and the like. Since the chip IO is usually placed on the edge of the chip, when the chip process develops below 10nm, the space f...

AI Technical Summary

Problems solved by technology

Since the chip IO is usually placed on the edge of the chip, when the chip manufacturing process develops below 10nm, the space for chip IO arrangement will be further reduced, which brings challenges to the chip IO arrangement, and the difficulty of chip IO arrangement will further increase. Large, the layout plan needs to be adjusted repeatedly, the workload is heavy, and human errors are prone to occur, the design cost is high, and the design cycle is long

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