Sampling compensation method and device of digital channel logic analyzer

Abstract

The invention provides a sampling compensation method and device for a digital channel logic analyzer. The method comprises the following steps: selecting a digital channel of a chip and outputting a digital signal to a service board; setting a sampling node based on a clock period; the first sampling unit samples the digital signal to obtain first sampling data; the delay carry chain delays the digital signal and outputs the delayed digital signal of each sub-chain to the second sampling unit; the second sampling unit samples the delayed digital signal and analyzes the digital signal to obtain compensation data; and according to whether the first sampling data and the second sampling data have level change, combining the compensation data to obtain a high-precision recovery signal of the digital signal. According to the scheme, high-resolution parallel sampling can be achieved, the real phase relation of digital signals can be restored through real sampling, narrow-pulse-width digital signal noise can be captured, limitation of the number of digital channels is avoided, extra hardware cost does not need to be increased, and the sampling cost is low.

Description

technical field [0001] The invention relates to the field of semiconductor chip testing, in particular to a sampling compensation method and device for a digital channel logic analyzer. Background technique [0002] ATE (Automatic Test Equipment) is an integrated circuit automatic test equipment, which is a special equipment used to detect the function and performance of chips. The DIO digital channel is the core functional module of the integrated circuit test equipment, which is responsible for the work of generating digital waveforms in chip testing and outputting them to the chip and receiving the digital signals output by the chip and comparing and judging. [0003] In the actual chip test, due to the various uncertainties in the actual output signal of the chip to be tested, when the automated test equipment fails to compare the signal received by the digital channel with the expected signal, it is necessary to perform physical analysis on the digital signal output by ...

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Problems solved by technology

[0008] The high-speed interface sampling method is to connect the digital signal to the high-speed transmission interface (GTP) of the FPGA for sampling, and the sampling rate can reach tens of GHZ. However, the high-speed transmission interface of the FPGA is limited and expensive, and cannot meet the channel number requirements of the test equipment.

[0009] The external multi-channel delay sampling method is often used in the design of high-speed analog oscilloscopes. In this method, the signal is fanned out into multiple signals, and each signal is delayed according to the law, and the multiple delayed signals are sampled and processed. The sampling signal is obtained by interpolation. This method is not only because of the high cost of the external delay chip, but also the delayed signal requires a large number of pins to be input to the FPGA for sampling, and the digital pins of the semiconductor test equipment are connected to the FPGA after passing through the PE chip in a fixed form. Therefore, this method cannot be directly introduced into the digital channel logic analyzer of semiconductor test equipment

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