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FPGA code defect positioning method and system based on program spectrum technology

A code defect and positioning method technology, applied in the field of hardware testing, can solve problems such as locating arithmetic symbol errors and conditional statement errors, and achieve the effects of reducing the number, high testing efficiency, and improving testing efficiency

Pending Publication Date: 2022-07-22
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, locating arithmetic symbol errors or conditional statement errors through static analysis including model-based methods is a big challenge due to the nature of static analysis

Method used

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  • FPGA code defect positioning method and system based on program spectrum technology
  • FPGA code defect positioning method and system based on program spectrum technology
  • FPGA code defect positioning method and system based on program spectrum technology

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] Embodiment 1: FPGA code defect location method based on program spectrum technology, such as figure 1 shown, including the following steps:

[0051] S1: Build a test set containing all test cases for defect location testing of the target program;

[0052] S2: Test the dynamically executed target program sequentially with the test cases in the test set to obtain the test result;

[0053] S3: Calculate the suspicious value of each program statement in the target program according to the test result corresponding to the test case that has been tested;

[0054]S4: If the suspicious value of the program statement is greater than the positioning threshold, output the corresponding program statement as the code defect positioning result of the target program; if not, continue to execute the next test case for testing.

[0055] The invention tests the dynamically executed defective target program through test cases, and locates the single defect existing in the target program...

Embodiment 2

[0071] Embodiment 2: FPGA code defect location method based on program spectrum technology, such as figure 2 As shown, the difference between Embodiment 2 and Embodiment 1 is that: in order to further reduce the number of test cases to run, the method further includes: determining, according to the defect type of the target program, the proportion of execution statements of the corresponding category in the test cases that have been tested. The positioning threshold is dynamically updated according to the proportion of executed statements of each test case and the number of test cases that have been tested.

[0072] The update process of the proportion of executed statements is as follows: determine the range of marked values ​​according to the defect type of the target program; filter out the number of executed statements whose marked values ​​are within the marked value range from the test cases; The ratio of the total number of executed statements is taken as the proportio...

Embodiment 3

[0076] Embodiment 3: an FPGA code defect location system based on program spectrum technology, the code defect location system is used to implement the code defect location method recorded in Embodiment 1 or Embodiment 2, such as image 3 As shown, including use case building module, dynamic testing module, suspicious value calculation module and location analysis module.

[0077] Among them, the use case building module is used to construct a test set containing all test cases for defect location testing of the target program; the dynamic test module is used to sequentially test the dynamically executed target program with the test cases in the test set to obtain the test results. ; The suspicious value calculation module is used to calculate the suspicious value of each program statement in the target program according to the test result corresponding to the test case that has been tested; Then output the corresponding program statement as the code defect location result of ...

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Abstract

The invention discloses an FPGA (Field Programmable Gate Array) code defect positioning method and system based on a program spectrum technology, and relates to the technical field of hardware testing, and the technical scheme is characterized by comprising the following steps of: constructing a test set which is used for carrying out defect positioning test on a target program and comprises all test cases; sequentially testing the dynamically executed target programs by using the test cases in the test set to obtain a test result; calculating a suspicious value of each program statement in the target program according to a test result corresponding to the test case of which the test is completed; if the suspicious value of the program statement is greater than the positioning threshold, outputting the corresponding program statement as a code defect positioning result of the target program; and if not, continuing to execute the next test case for testing. According to the method, the defects of a static analysis method in hardware code defect positioning are effectively overcome, meanwhile, all test cases do not need to be operated for testing, and the test efficiency is effectively improved.

Description

technical field [0001] The invention relates to the technical field of hardware testing, and more particularly, to a method and system for locating FPGA code defects based on program spectrum technology. Background technique [0002] HDL (Hardware Description Language) is a language for describing digital circuits and systems using a formal method. According to statistics, more than 90% of ASICs and FPGAs are currently designed with HDL. HDL has been successfully used in all stages of design: modeling, simulation, verification, and synthesis. To date, hundreds of hardware description languages ​​have emerged, greatly facilitating design automation. Today's production use of source-code-based approaches enables designers to create very complex systems-on-chips that use source code as the basis for logic synthesis. Recent achievements in formal verification techniques allow even defect detection in large real-world designs, where tool support for localizing erroneous statem...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F11/36
CPCG06F11/2273G06F11/3684
Inventor 徐建军毛晓光吴江张卓杨德亨何枷瑜李盼盼
Owner NAT UNIV OF DEFENSE TECH