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Semiconductor structure and forming method thereof

A technology of semiconductor and gate structure, applied in the field of semiconductor structure and its formation, can solve problems such as performance degradation of semiconductor structure, and achieve the effect of improving performance

Pending Publication Date: 2022-07-26
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, in the prior art, when the long-channel gate structure and the short-channel gate structure coexist in the semiconductor structure, other problems will also occur, which will reduce the performance of the final semiconductor structure.

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0032] As described in the background art, when the long-channel gate structure and the short-channel gate structure coexist in the semiconductor structure, other problems also arise, which degrades the performance of the finally formed semiconductor structure. The following will be described in detail with reference to the accompanying drawings.

[0033] Please refer to figure 1 , a substrate 100 is provided, the substrate 100 includes a first region I and a second region II, the first region I has a plurality of mutually discrete first fins 101, and the second region II has a plurality of mutually separated first fins 101 Discrete second fins 102, the first fins 101 and the second fins 102 respectively extend along the first direction X; form a plurality of first gate structures 103, a plurality of second gate structures 104, a plurality of A source-drain doped layer 105, a plurality of second source-drain doped layers 110 and a first dielectric layer 106, the first gate s...

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Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region and a second region, the first region is provided with a first fin part, and the second region is provided with a second fin part; a first gate structure, a second gate structure, a first source-drain doping layer, a second source-drain doping layer and a first dielectric layer, wherein the top surface of the first dielectric layer on the first region is lower than the top surface of the first dielectric layer on the second region; the first barrier layer is positioned on the first dielectric layer on the first region; the first opening is located in the first barrier layer and the first dielectric layer on the first region, and the second opening is located in the first dielectric layer on the second region. Due to the fact that the etching rate of the first barrier layer is smaller than that of the first dielectric layer, in the process of forming the first opening, certain etching time is consumed through the first barrier layer, the time for finally etching the first source-drain doping layer is shortened, etching penetrating through the first source-drain doping layer is avoided, and the performance of the finally-formed semiconductor structure is improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the improvement of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, and the reduction of the critical dimension means that a larger number of transistors can be arranged on a chip, thereby improving the performance of the device. However, as device areas continue to shrink, problems also arise. With the sharp reduction of the size of the transistor, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, which makes it more difficult to suppress the short-channel effect and increases the channel leakage current of the transistor. [0003] The MOS tube shrinks and the gate becomes shorter, so that the current channel under the gate also becomes shor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/423H01L21/336
CPCH01L29/66803H01L29/785H01L29/42356H01L21/3212H01L21/823431H01L29/41791H01L27/0886H01L29/66545H01L21/823456H01L21/823418H01L29/41775H01L29/42376
Inventor 纪登峰金懿
Owner SEMICON MFG INT (SHANGHAI) CORP