Iterative model establishment method and simulation method of cross-point storage array

A storage array and model building technology, applied to CAD circuit design, etc., can solve the problems of high simulation overhead, high time complexity and space complexity, and low simulation efficiency, so as to reduce simulation overhead, improve simulation efficiency, and reduce time The effect of space complexity

Pending Publication Date: 2022-07-29
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

[0007] In general, the traditional method establishes a model of the cross-point storage array based on linear equations, and performs simulation based on this model, which has high time complexity and space complexity, low simulation efficiency, and high simulation overhead

Method used

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  • Iterative model establishment method and simulation method of cross-point storage array
  • Iterative model establishment method and simulation method of cross-point storage array
  • Iterative model establishment method and simulation method of cross-point storage array

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Embodiment 1

[0048] An iterative model building method for a cross-point storage array; in this embodiment, the cross-point storage array uses the high and low values ​​of memory cell resistances to represent stored information, and the total number of word lines m and the total number of bit lines n of the cross-point storage array satisfy :

[0049] In this embodiment, the method for establishing an iterative model of a cross-point storage array includes: for a target memory cell located at (x, y) in the cross-point storage array, establishing the following iterative model based on Kirchhoff's voltage law:

[0050]

[0051] Among them, x and y respectively represent the number of the word line and bit line where the target memory cell is located, 1≤x≤m, 1≤y≤n; represents the voltage applied on the word line where the target memory cell is located, Represents the voltage applied on the bit line where the target memory cell is located; r wl Represents the line resistance between t...

Embodiment 2

[0089] A method for simulating a cross-point storage array, this embodiment is proposed based on the method for establishing an iterative model of a cross-point storage array provided in the above-mentioned Embodiment 1, refer to image 3 and Figure 4 , this embodiment includes the following steps:

[0090] (S1) Initialize the voltage of each node in the cross-point memory array according to the word line voltage and bit line voltage to be applied, and form a voltage matrix V by the voltage of the upper node of each memory cell up , the voltage matrix V is formed by the voltage of the lower node of each memory cell down , and initialize the current number of iterations to k=1;

[0091] The upper node of the storage unit is the node formed by the intersection of the storage unit and the word line where it is located, and the lower node of the storage unit is the node formed by the intersection of the storage unit and the bit line where it is located;

[0092] As an optional...

Embodiment 3

[0114] A method for simulating a cross point memory array, this embodiment is similar to the above-mentioned Embodiment 2, the difference is that in step (S1) of this embodiment, according to the word line voltage and the bit line voltage to be applied, the cross point is initialized The voltage of each node in the point storage array, including:

[0115] According to the word line voltage and bit line voltage to be applied, and the conductance matrix G of each memory cell, the corresponding node initial voltage matrix is ​​searched from the pre-established mapping table, and the corresponding initial voltage matrix of each node is initialized according to the node initial voltage matrix. Voltage;

[0116] The node initial voltage matrix is ​​used to record the initial voltage value of each node in the simulation process, and the mapping table is used to record the correspondence between the combination of word line voltage, bit line voltage and conductance matrix and the node...

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Abstract

The invention discloses an iterative model establishment method and a simulation method of a cross point storage array, and belongs to the field of information storage and storage calculation integration, and the model is as follows: the simulation method comprises the following steps: (S1) initializing the voltage of each node in the array, and respectively forming a voltage matrix Vup and a voltage matrix Vdown by the voltages of the upper node and the lower node of each storage unit; (S2) calculating the current of each storage unit in the (k-1) th iteration according to Iarr [k-1] = Gcircle (Vup-Vdown), and calculating the total current flowing through each word line and each bit line; (S3) updating the upper node voltage and the lower node voltage of each storage unit in the k-th iteration so as to update Vup and Vdown; and (S4) iteratively executing the steps (S2)-(S3) until the error of the k-th iteration is smaller than epsilon than that of the last iteration, or the maximum number of iterations is reached. According to the invention, the time and space complexity of simulating the cross point array can be reduced.

Description

technical field [0001] The invention belongs to the field of information storage and storage-computation integration, and more particularly, relates to an iterative model establishment method and a simulation method of a cross-point storage array. Background technique [0002] Resistive memory, magnetoresistive memory, phase change memory, etc., use the high and low values ​​of the resistance of the memory cell to represent the stored information. In these memories, the memory cell is sandwiched between the word line and the bit line to construct a cross-point memory array, in which , Resistive memory is the most commonly used cross-point memory array. Applying forward or reverse pulses exceeding a certain amplitude to both ends of the memory cells of the cross-point memory array can change the resistance value of the memory cells, while applying a small read voltage to it, the memory can be judged by the magnitude of the outflow current. resistance value. Due to the exist...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/36
CPCG06F30/36
Inventor 冯丹吴兵童薇刘锦鹏程欢周恒
Owner HUAZHONG UNIV OF SCI & TECH
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