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Semiconductor device including separation pattern and electronic system

A semiconductor and device technology, applied in the field of semiconductor devices including separation patterns and electronic systems, can solve problems such as process difficulties

Pending Publication Date: 2022-07-29
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the integration of three-dimensionally arranged memory cells increases, the process of forming these cells becomes increasingly difficult

Method used

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  • Semiconductor device including separation pattern and electronic system
  • Semiconductor device including separation pattern and electronic system
  • Semiconductor device including separation pattern and electronic system

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0017] figure 1 and figure 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. image 3 The layout of a semiconductor device according to an embodiment of the present disclosure is shown. Figure 4 is shown image 3 A partial view of a part of the . Figure 5 is shown figure 1 Partial view of part 8. In an embodiment of the present disclosure, figure 1 can be along image 3 Sectional view taken on line 5-5' in, figure 2 can be along image 3 A cross-sectional view taken on line 6-6' in . In embodiments of the present disclosure, the semiconductor device may include non-volatile memory, such as vertical NAND (VNAND) or three-dimensional (3D) flash memory. The semiconductor device according to an embodiment of the present disclosure may further include a cell-on-periphery (COP) structure.

[0018] refer to figure 1 , the semiconductor device according to the embodiment of the present disclosure may include a s...

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PUM

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Abstract

A semiconductor device including a separation pattern and an electronic system are provided. The semiconductor device includes: a horizontal wiring layer; a stacked structure including a plurality of mold layers and a plurality of wiring layers alternately stacked on the horizontal wiring layer; a plurality of channel structures extending through the stack structure; and a plurality of separation patterns extending through the stacked structure, where each of the plurality of separation patterns includes a plurality of first portions and a plurality of second portions adjacent to the plurality of first portions, where each of the plurality of first portions has a smaller width than each of the plurality of second portions.

Description

technical field [0001] Embodiments of the present disclosure relate to a semiconductor device including a word line separation pattern, an electronic system including the semiconductor device, and a method of forming the semiconductor device. Background technique [0002] In electronic systems that store large amounts of data, semiconductor devices with large data storage capacities are required. One of the devices used to increase the data storage capacity of semiconductor devices is a three-dimensionally arranged integrated circuit. For example, such semiconductor devices include vertically stacked and interconnected memory cells. However, as the integration of three-dimensionally arranged memory cells increases, the process of forming these cells becomes increasingly difficult. SUMMARY OF THE INVENTION [0003] Embodiments of the present disclosure provide a semiconductor device capable of preventing deformation of a multilayer structure, an electronic system includin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11565H01L27/1157H01L27/11573H01L27/11575H01L27/11582
CPCH10B43/35H10B43/10H10B43/50H10B43/40H10B43/27H01L2224/32225H01L2224/48145H01L2924/181H01L2924/15311H01L2224/32145H01L2224/08145H01L25/18H01L25/0657H01L2924/00012H01L24/08
Inventor 申重植
Owner SAMSUNG ELECTRONICS CO LTD